OLED Pixel Capacitor Stack for High Charge Capacity

The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by placing multiple conductive layers (first, second, third, and fourth conductive layers) at different vertical positions. This vertical stacking enables multiple capacitive elements to occupy the same planar footprint, thereby increasing charge capacity without expanding the pixel area.

The patent embeds multiple conductive layers within each other in a vertical stack, where the first conductive layer is disposed on the substrate, the second conductive layer is interposed between the substrate and the first conductive layer, and the third and fourth conductive layers are disposed facing each other. This nested arrangement maximizes the use of vertical space within the pixel area.

By utilizing the vertical dimension through multiple stacked conductive layers, the patent achieves high charge capacity within a reduced planar footprint, enabling high resolution display while maintaining sufficient capacitor size.

The capacitor is segmented into multiple discrete conductive layers (first, second, third, and fourth layers) that can be independently formed and positioned. This segmentation allows each layer to contribute to the overall charge capacity while maintaining a compact planar structure.

The patent combines multiple conductive layers and insulating layers into a unified stacked capacitor structure that functions as a single integrated component. This merging approach increases charge capacity while managing complexity through systematic integration of layers.

The stacked conductive layers serve multiple functions: they form capacitive elements for charge storage, provide electrical connections, and can be integrated with surrounding transistor structures. This multi-functionality reduces overall device complexity by consolidating multiple functions into a single structure.