OLED Display Panel Cathode Network for Uniform Low-Voltage Supply
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Solution Overview
Problem
Existing OLED display panels face challenges in maintaining uniform voltage distribution and reducing voltage drops, leading to issues like high current concentration and potential burns, especially in large panels, due to the lack of an interconnected low voltage supply network.
Innovation Solution
The implementation of an interconnected low voltage supply network with signal lines in the display area and a peripheral area, where the low voltage signal lines are connected through vias in the planarization layer, providing a stable low voltage signal to cathodes of light emitting elements and reducing the need for vias in the display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional low voltage supply network is used without interconnection, then the fabrication process is simpler, but voltage drops increase by over 20% and current concentration causes burns
Solution Approach 1:
The low voltage supply network is segmented into multiple independent low voltage lines (first low voltage line, second low voltage line, etc.) that are distributed across different signal line layers. Each line independently supplies low voltage to specific regions, preventing current concentration and reducing voltage drops without requiring a fully interconnected complex network.
Solution Approach 2:
The patent utilizes multiple signal line layers (first signal line layer, second signal line layer) to distribute low voltage lines in three-dimensional space. This vertical dimensionality allows low voltage supply paths to be established without increasing planar complexity, reducing voltage drops while maintaining a manageable network structure.
2Reliability
If vias are extensively used in the display area to connect low voltage lines, then voltage uniformity improves, but the fabrication process becomes more complex and bezel width increases
Solution Approach 1:
The patent moves low voltage line connections from the planar display area into the vertical dimension by using multiple signal line layers. Low voltage lines are connected through vias between layers rather than through the display area, reducing the number of display-area vias needed and simplifying fabrication while maintaining voltage uniformity.
Solution Approach 2:
The planarization layer serves as an intermediary structure that facilitates low voltage line connections. By routing low voltage lines through different signal line layers and using the planarization layer for via connections, the patent reduces the need for extensive vias in the display area while achieving uniform voltage distribution.
3Ease of manufacture
If low voltage lines are concentrated in the peripheral area, then fabrication is simpler, but voltage drops increase and current concentration causes burns
Solution Approach 1:
The low voltage supply network is segmented into multiple distributed lines that extend from the peripheral area into the display area through different signal line layers. This segmentation allows the network to maintain fabrication simplicity while achieving better voltage distribution and preventing current concentration.
Solution Approach 2:
By utilizing multiple signal line layers, the patent extends low voltage supply capability from the peripheral area into the display area without increasing planar complexity. This vertical expansion maintains fabrication simplicity while improving voltage stability throughout the display area.
Data Source
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AI summary
A display panel is provided. The display panel includes a plurality of light emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements. The interconnected first voltage supply network includes signal lines in a display area (DA) of the display panel, the display area (DA) being at least partially surrounded by a peripheral area (PA). The signal lines include a plurality of first signal lines (Vss1) in a first signal line layer (SL1) and a plurality of second signal lines (Vss2) in a second signal line layer (SL2). The display panel further includes a planarization layer (PLN1) between the first signal line layer (SL1) and the second signal line layer (SL2). The plurality of first signal lines (Vss1) are electrically connected to the plurality of second signal lines (Vss2).