OLED Display Clock Signal Routing and Delay Reduction
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Solution Overview
Problem
Conventional OLED displays face challenges in minimizing clock signal delay, increasing production costs, and reducing production yield due to the need for multiple flexible printed circuits to provide clock signals, which complicates the manufacturing process.
Innovation Solution
The OLED display design includes a panel with a data driver and a gate driver connected in an insulated manner, featuring a first connecting line overlapped on a second electrode and a second connecting line not overlapped on the second electrode, with a third connecting line extending to connect the second connecting line to the first connecting line, reducing signal delay and eliminating the need for additional flexible printed circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple flexible printed circuits are installed to provide clock signals, then clock signal delay is reduced, but production cost increases and production yield deteriorates
Solution Approach 1:
The patent combines multiple clock signal input functions into a single input line by using switching elements within the gate driver. Instead of requiring multiple separate flexible printed circuits, the system merges the clock signal distribution through internal switching, reducing external connections while maintaining proper signal timing to different regions.
Solution Approach 2:
The patent introduces switching elements as intermediaries between the single clock signal input and the various gate lines. These switching elements act as mediators that receive the clock signal and distribute it to different regions at appropriate times, eliminating the need for multiple direct clock signal connections from external circuits.
2Loss of time
If multiple flexible printed circuits are installed to provide clock signals, then clock signal delay is reduced, but production cost increases
Solution Approach 1:
The patent combines multiple clock signal input functions into a single input line by using switching elements within the gate driver. Instead of requiring multiple separate flexible printed circuits, the system merges the clock signal distribution through internal switching, reducing external connections while maintaining proper signal timing to different regions.
Solution Approach 2:
The patent replaces expensive multiple flexible printed circuits with a simpler, more cost-effective design using standard input lines and integrated switching elements. This substitution uses more economical components and manufacturing approaches while achieving the same functional result of reducing clock signal delay.
3Loss of time
If the connecting line is overlapped on the cathode to form a capacitor, then signal timing is delayed, but signal transmission is improved
Solution Approach 1:
The patent uses dynamic switching elements that can change their state based on timing requirements. Instead of static capacitor structures that permanently delay signals, the switching elements dynamically control signal transmission timing, allowing the system to adjust when signals are passed to different regions without relying on fixed capacitive delay structures.
Solution Approach 2:
The patent changes the operational parameters of the connecting lines by using active switching elements rather than passive capacitive structures. The switching elements can modify their conductive state to control signal timing, replacing the fixed delay characteristic of capacitors with controllable, adjustable timing parameters.
Data Source
AI summary
An organic light emitting diode display includes: a panel; a data driver connected to a data line formed on the panel; a gate driver crossing the data line in an insulated manner and connected to gate lines formed on the panel; an input line for receiving clock signals from the outside; a first connecting line electrically connected to the input line to supply the clock signal to the gate driver; a second connecting line electrically connected to the input line; and a third connecting line extended from the second connecting line to electrically connect the second connecting line and the first connecting line.