OLED Substrate Clock Wiring for Impedance Matching
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Solution Overview
Problem
In OLED display panels, impedance differences between clock signal lines connected to adjacent shift registers cause periodic horizontal stripes, affecting display quality due to varying signal falling edges and brightness.
Innovation Solution
The display substrate is designed with a specific wiring sequence for clock signal lines, ensuring impedance differences between adjacent groups are less than or equal to a threshold value, eliminating the impedance mismatch and aligning signal falling edges for uniform brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If clock signal lines are connected to shift registers in conventional wiring sequence, then the circuit structure is simple, but impedance differences cause periodic horizontal stripes affecting display quality
Solution Approach 1:
The patent applies asymmetry by changing the conventional sequential wiring order of clock signal lines to a specific asymmetric sequence (e.g., 1-3-5-7-2-4-6-8 or 1-5-2-6-3-7-4-8). This asymmetric reordering balances the impedance distribution across adjacent shift registers, eliminating the periodic impedance differences that cause horizontal stripes while maintaining circuit functionality.
Solution Approach 2:
The patent changes the wiring sequence parameter of clock signal lines from conventional sequential order to a specifically designed non-sequential order. This parameter change redistributes the impedance characteristics along the signal lines, ensuring that adjacent shift registers receive clock signals with matched impedance values, thereby eliminating display artifacts.
2Illumination intensity
If impedance differences between clock signal lines are large, then wiring design is simple, but signal falling edges vary causing brightness non-uniformity
Solution Approach 1:
The asymmetric wiring sequence redistributes clock signal line connections to balance impedance values across all shift registers. This ensures that signal falling edges occur at consistent time points, producing uniform brightness across the display panel without requiring complex additional circuitry.
3Manufacturing precision
If conventional wiring sequence is used, then manufacturing process is simple, but periodic horizontal stripes appear reducing display quality
Solution Approach 1:
The asymmetric wiring sequence can be directly implemented in the PCB layout or flexible circuit board design without requiring additional manufacturing steps. The sequence itself (e.g., 1-3-5-7-2-4-6-8) provides the impedance balancing effect, eliminating horizontal stripes while maintaining manufacturing simplicity through direct integration into existing wiring processes.
Data Source
AI summary
Disclosed is a display substrate and a display apparatus, the display substrate includes a display area and a peripheral area, wherein the display substrate includes M groups of shift registers and N groups of clock signal lines in the peripheral area, M is greater than or equal to N, M and N are positive integers, each group of shift registers is connected with a group of gate lines positioned in the display area, and adjacent N groups of shift registers are connected with N groups of clock signal lines one by one correspondingly. The N groups of clock signal lines are disposed side by side along a first direction, and configured to make, through an adjustment of a wiring sequence, an impedance difference between two groups of clock signal lines connected to any two adjacent groups of shift registers be less than or equal to an impedance threshold value.