High Aperture Ratio OLED Display With Extraction Compensation Transistor

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Solution Overview

Problem

Existing ultra high density organic light emitting diode displays face challenges in maintaining high aperture ratio and video quality due to signal delay caused by increased load on scan lines, which is exacerbated by the presence of compensation elements and complex thin film transistor structures.

Innovation Solution

Incorporating a compensation thin film transistor to detect pixel degradation and reduce the number of lines overlapping with scan lines, thereby minimizing parasitic capacitance and allowing for simultaneous activation of all switching thin film transistors without signal delay, ensuring superior video quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the number of lines overlapping with scan lines is increased to provide more functionality, then device complexity increases, but signal delay increases and video quality deteriorates

Engineering Contradiction:
Improvenumber of linesVSAvoidsignal delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent extracts the compensation function from the traditional pixel circuit structure and implements it using a separate compensation thin film transistor positioned in the non-emission area. This separation removes the harmful overlapping between compensation lines and scan lines, eliminating parasitic capacitance while preserving the compensation function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent relocates the compensation thin film transistor from the traditional in-pixel position to the non-emission area, effectively moving it to a different spatial dimension. This repositioning allows the compensation circuit to operate independently without interfering with the scan line signal path, thus resolving the signal delay issue.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If ultra high density is achieved by reducing pixel pitch, then area utilization improves, but line load increases causing signal delay

Engineering Contradiction:
Improveaperture ratioVSAvoidsignal delay
Core Design Contradiction:
Area of stationary objectVSLoss of time

Solution Approach 1:

The patent segments the display area into emission area and non-emission area, and strategically places the compensation thin film transistor in the non-emission area. This segmentation allows the scan lines to operate independently without carrying additional compensation signals, thereby reducing line load and eliminating signal delay while maintaining high aperture ratio.

Inventive Principle:
Principle #1Segmentation

3Reliability

If compensation elements are added to detect pixel degradation, then reliability improves, but device complexity and line load increase

Engineering Contradiction:
Improvepixel degradation detectionVSAvoidcompensation circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The compensation thin film transistor is configured to automatically detect pixel degradation through its gate voltage changes and self-adjust the pixel circuit parameters accordingly. This self-service mechanism eliminates the need for complex external compensation circuits and additional control lines, maintaining reliability while simplifying device complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3324392B1Large area ultra high density flat display having high aperture ratio
Publication Date: 2022.04.06 LG DISPLAY CO LTD
  • EP3324392B1 patent drawingFigure 1~2
  • EP3324392B1 patent drawingFigure 3
  • EP3324392B1 patent drawingFigure 4

AI summary

The present disclosure relates to a large area ultra high density flat panel display having high aperture ratio. The present disclosure provides a flat panel display comprising: a driving current line (VDD) and a sensing line (REF) disposed in a first direction on a substrate; a scan line (SL) and a sensing gate line (EL) disposed in a second direction on the substrate; a horizontal current line (VDDh) disposed at upper side of the scan line (SL) in the second direction and connected to the driving current line (VDD); a horizontal sensing line (REFh) disposed at lower side of the sensing gate line (EL) in the second direction and connected to the sensing line (REF); a common current line (VDDc) branched from the horizontal current line (VDDh) and crossing the scan line (SL); and a first pixel area and a second pixel area disposed between the driving current line (VDD) and the sensing line (REF) as having a bi-symmetic shape with each other based on the common current line (VDDc).