OLED Display Contact Hole Layout With Single-Photomask Etching

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Solution Overview

Problem

The existing manufacturing methods for organic light emitting diode (OLED) displays face challenges in efficiently forming multiple contact holes in various insulation layers without increasing manufacturing costs, which can lead to complex and costly photolithography processes.

Innovation Solution

The proposed solution involves a display device structure that includes an etching prevention layer with a hole aligned vertically with sub-contact holes in the insulation layers, allowing for the formation of contact holes using a single photomask, thereby reducing the number of masks required and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple contact holes are formed in various insulation layers using conventional photolithography methods, then the contact holes can be formed with good alignment, but the manufacturing process becomes complex and costly due to the need for multiple masks

Engineering Contradiction:
Improvecontact hole alignmentVSAvoidphotolithography process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the formation of multiple contact holes across different insulation layers into a single photolithography step. By using one photomask to define all contact hole positions simultaneously, the method combines what would traditionally require multiple separate lithography steps into one unified process, reducing complexity while maintaining alignment precision

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single photomask serves multiple functions by defining contact holes for different insulation layers at different spatial locations. This universal mask design allows one mask to perform the work of multiple masks, enabling the formation of all contact holes across the device structure in a single exposure and development cycle

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple photomasks are used to form contact holes in different insulation layers, then each contact hole can be precisely formed, but the manufacturing cost increases

Engineering Contradiction:
Improvecontact hole formation precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent combines multiple mask-based contact hole formation steps into a single lithography step. By consolidating the patterning function into one mask and one exposure process, the method eliminates the need to purchase, store, and process multiple photomasks, directly reducing manufacturing costs while preserving the precision needed for contact hole formation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single photomask creates a copied pattern that is transferred to multiple insulation layers through the etching process. Instead of using different masks for each layer, the same mask pattern is effectively copied and transferred to different layers at different locations, reducing the number of physical masks needed

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11925098B2Display device and manufacturing method thereof
Publication Date: 2024.03.05 SAMSUNG DISPLAY CO LTD
  • US11925098B2 patent drawing
  • US11925098B2 patent drawing
  • US11925098B2 patent drawing

AI summary

A display device includes a first transistor including a first active layer, a first gate electrode overlapping the first active layer, a gate insulating layer between the first active layer and the first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second active layer, a second gate electrode overlapping the second active layer, a second source electrode and a second drain electrode; a capacitor including a first capacitor electrode connected to the second transistor; a lower electrode disposed under the first active layer; a connecting member connecting the first active layer to the lower electrode; and a first metal pattern contacting the connecting member and disposed on a same layer with the first gate electrode.