OLED Pixel Data Line Crosstalk Reduction via Transistor Routing
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Solution Overview
Problem
OLED displays face issues with row-to-row data crosstalk due to parasitic coupling capacitance between data lines and drive transistor circuitry, leading to inaccurate light emission as data signals from one pixel row inadvertently couple to adjacent rows.
Innovation Solution
The design includes a data loading transistor with a channel region extending in a first direction and drive transistor circuitry with channel regions in a second direction, both formed using silicon traces connected in series with a portion that includes 90-degree bends, and metal shielding layers covering the transistors to reduce parasitic coupling, ensuring the data line does not overlap with the source region of the data loading transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the data line is routed directly over the source region of the data loading transistor for compact layout, then the pixel area is reduced, but row-to-row data crosstalk increases due to parasitic coupling capacitance
Solution Approach 1:
The data line is extracted from its conventional position directly over the source region and routed instead over the drain region. This spatial separation removes the harmful parasitic coupling capacitance between the data line and source region, eliminating the source of row-to-row crosstalk while preserving the compact pixel layout through optimized routing paths.
Solution Approach 2:
The drain region serves as an intermediary routing path for the data line. By positioning the data line over the drain region rather than directly over the source region, the design uses the drain region as a mediating structure that allows compact routing without creating harmful capacitive coupling, thus reducing crosstalk while maintaining area efficiency.
2Manufacturing precision
If the channel regions of data loading transistor and drive transistor circuitry are formed perpendicular to each other using silicon traces, then manufacturing precision is improved, but the trace length and complexity increase
Solution Approach 1:
The channel regions of the data loading transistor and drive transistor circuitry are arranged in perpendicular directions (first direction and second direction). This dimensional change from collinear to perpendicular arrangement improves manufacturing precision by reducing alignment sensitivity, while the use of 90-degree bends in the silicon trace routing manages the increased complexity through standardized geometric transitions.
Solution Approach 2:
The silicon trace connecting the perpendicular channel regions incorporates 90-degree bends to navigate between orthogonal directions. These standardized angular transitions manage the routing complexity by using precise geometric features that are manufacturable with standard fabrication processes, transforming the complexity challenge into a controlled geometric design.
Data Source
AI summary
A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.