OLED Array Detection Line Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In OLED display panels, the existing array substrates face challenges with high parasitic capacitance and yield issues due to the overlap of detection lines and data lines, which affect signal transmission efficiency and product yield.
Innovation Solution
The array substrate design alternately shares detection line structures between adjacent rows of subpixels, reducing the number of detection lines and overlap with data lines, thereby minimizing parasitic capacitance and improving product yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detection lines are provided for each row of subpixels, then detection coverage is improved, but parasitic capacitance increases and yield decreases
Solution Approach 1:
The patent merges detection lines by having a single detection line serve multiple adjacent rows of subpixels simultaneously. The detection line is positioned to extend across the boundary between two subpixel row groups and electrically connect to subpixels in both groups, thereby combining detection functions that would traditionally require separate lines for each row.
Solution Approach 2:
The detection line structure is designed to perform multiple detection functions across different subpixel rows. A single detection line structure can detect electrical characteristics (such as threshold voltage) of transistors in multiple adjacent rows, making it a multi-functional component that replaces what would traditionally require multiple separate detection lines.
2Adaptability or versatility
If detection lines overlap with data lines, then routing flexibility is improved, but signal transmission quality deteriorates
Solution Approach 1:
The patent extracts the detection line function from the data line routing path. By providing detection lines that are separate from and do not overlap with data lines, the detection function is taken out of the data transmission path, eliminating the harmful overlap while maintaining routing flexibility through the dedicated detection line structure.
3Object-affected harmful factors
If number of detection lines is reduced, then parasitic capacitance is reduced, but detection coverage may be insufficient
Solution Approach 1:
The patent extends the detection line in the vertical dimension to span across multiple subpixel rows. Instead of having short horizontal detection segments for each row, the detection line is extended vertically to cover multiple rows, thereby maintaining comprehensive detection coverage while using fewer total detection lines and reducing parasitic capacitance.
Data Source
AI summary
An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of signal line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each signal line structure of the plurality of signal line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, and the signal line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.