OLED Display Panel Storage Capacitor Vertical Integration
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Solution Overview
Problem
Large-sized OLED display devices face a low aperture ratio due to the space occupied by storage capacitors in their pixel structure, which affects their performance.
Innovation Solution
The solution involves a display panel design where the storage capacitor is formed on a package substrate instead of the array substrate, with electrodes and conductive pillars strategically positioned to maximize the effective area without occupying space on the array substrate, allowing for improved aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage capacitor is formed on the array substrate using metal layers, then the capacitor can be integrated into the pixel structure, but the aperture ratio is significantly reduced due to the occupied area
Solution Approach 1:
The storage capacitor is relocated from the array substrate (2D plane) to the package substrate (3D space above the array substrate). The first electrode is positioned above the array substrate, and the second electrode is on the package substrate, creating a vertical capacitor structure that eliminates the area occupation problem on the array substrate while maintaining capacitor integration.
2Ease of manufacture
If the storage capacitor electrodes are positioned between adjacent transistors along the data signal line direction, then the capacitor can be formed using existing metal layers, but a certain area is occupied which affects the aperture ratio
Solution Approach 1:
The capacitor structure transitions from a planar arrangement on the array substrate to a vertical arrangement spanning the array substrate and package substrate. The first electrode extends above the array substrate and the second electrode is on the package substrate, utilizing the third dimension to eliminate area occupation while maintaining manufacturability through existing metal layer processes.
3Reliability
If the first electrode is positioned on the array substrate to connect to the driving transistor, then electrical connection is achieved, but the area available for light emission is reduced
Solution Approach 1:
The first electrode is repositioned from the array substrate plane to a location above the array substrate. This vertical displacement allows the electrode to maintain electrical connection functionality while being removed from the light emission plane, thereby increasing the effective area without compromising electrical connectivity.
Data Source
AI summary
A display panel includes an array substrate and a package substrate disposed opposite to each other, wherein, the array substrate includes a plurality of pixel units arranged in an array, and at least one of the pixel units includes a driving transistor. Further, the package substrate includes a first electrode and a second electrode disposed opposite to each other and an insulating layer located between the two electrodes. Wherein, the first electrode is electrically connected to the first terminal of the driving transistor, and the second electrode is electrically connected to the control terminal of the driving transistor.