OLED Display Module Frame Reduction via Circuit Inversion
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Solution Overview
Problem
The existing OLED display modules are limited by the frame size due to the specific circuit arrangement, which restricts further reduction and leads to non-uniform display and parasitic capacitance issues affecting signal transmission.
Innovation Solution
Interchanging the positions of the control emission circuit (EM) element and EM clock signal line (Clk) allows the low-potential VSS to cover the EM element, reducing impedance and enabling a narrower frame while maintaining original impedance, thereby increasing the available line width and improving display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the control emission circuit element and EM clock signal line are arranged in the conventional layout, then the circuit structure is simple, but the frame size cannot be reduced further and impedance of the emission layer VSS is high
Solution Approach 1:
The patent applies inversion by swapping the positions of the EM clock signal line and the control emission circuit element. The EM clock signal line is moved from its conventional position adjacent to the emission circuit element to a position closer to the low-potential port, while the control emission circuit element is relocated to where the clock signal line previously was. This positional inversion allows the low-potential VSS to cover the EM element, reducing impedance while enabling frame reduction.
Solution Approach 2:
The patent utilizes dimensional reorganization by arranging circuit elements in multiple layers and regions. The low-potential VSS is extended to cover the EM element in the vertical dimension, while the clock signal line is repositioned in the horizontal plane. This multi-dimensional arrangement allows simultaneous achievement of low impedance and compact frame size.
2Area of stationary object
If the frame is reduced to increase display area, then the display area increases, but the circuit arrangement becomes constrained and parasitic capacitance increases
Solution Approach 1:
The patent extracts the EM clock signal line from its conventional position near the emission circuit element and relocates it closer to the low-potential port. This extraction removes the source of parasitic capacitance from the critical emission circuit area, allowing for reduced frame size and increased display area without suffering from high parasitic capacitance effects.
Solution Approach 2:
The low-potential VSS serves as an intermediary element that is extended to cover the EM element. This intermediary arrangement provides a low-impedance path that compensates for the reduced spacing between circuit elements, allowing compact frame design while maintaining signal integrity and reducing parasitic capacitance effects.
3Reliability
If the low-potential VSS is extended to cover the EM element, then impedance is reduced, but the circuit layout becomes more complex
Solution Approach 1:
The patent merges the low-potential VSS extension with the existing circuit layout by having the VSS cover the EM element and connect to the low-potential port through the repositioned clock signal line area. This merging approach reduces impedance while integrating the layout changes seamlessly into the overall circuit design, minimizing the increase in complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the frame size of the OLED display module, enhances display uniformity, and decreases the impedance of the emission layer VSS, leading to improved stability and a more compact design.
Implementation Method 1
the active layer includes an organic electroluminescence material layer
Data Source
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AI summary
This application provides an OLED display module. The display module includes: a first region located in a substrate, where the first region is used to arrange a control element; a plurality of other regions located on both sides of the first region in the substrate, where the plurality of other regions are sequentially disposed based on distances from the first region, and the plurality of other regions sequentially include: a second region, used to arrange a first circuit element; a third region, used to arrange a first circuit clock signal line; a fourth region, used to arrange a second circuit clock signal line; a fifth region, used to arrange a second circuit element; and a sixth region, used to arrange a first low-potential port; a seventh region located on an upper surface of the substrate, where the seventh region covers the sixth region and partially covers the fifth region, and is used to arrange a second low-potential port, and the first low-potential port is electrically connected to the second low-potential port; and an eighth region located on the upper surface of the substrate, where the eighth region covers the seventh region and the upper surface of the substrate, and is used to arrange a third low-potential port.