OLED Display Semiconductor Extension for Crosstalk Reduction
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Solution Overview
Problem
High-resolution OLED displays face challenges in minimizing vertical crosstalk due to parasitic capacitance between the data line and the driving gate node, which affects luminance and resolution, and existing design limitations restrict further reduction in pixel size.
Innovation Solution
The OLED display incorporates a semiconductor layer with an extension overlapping the data line, positioned between the scan line and the data line, to minimize parasitic capacitance, and features a curved driving channel and multiple transistors for improved voltage control, allowing for a wider driving gate-source voltage range and enhanced gray scale control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the spacing between the data line and the driving gate node is increased to minimize parasitic capacitance, then vertical crosstalk is reduced, but the pixel size increases which limits resolution improvement
Solution Approach 1:
The patent introduces a new spatial dimension by adding a semiconductor layer extension that overlaps the data line in the vertical stacking direction. This allows the driving gate node to be positioned in a different vertical layer while maintaining horizontal proximity, thereby reducing parasitic capacitance without increasing pixel area.
Solution Approach 2:
The patent embeds the semiconductor layer extension within the existing pixel structure, nesting it between the data line and the driving gate node. This nested configuration allows the extension to shield the driving gate node from the data line's electric field without adding external space.
2Manufacturing precision
If the pixel size is reduced to increase resolution, then more pixels fit in the display area, but the spacing between data line and driving gate node decreases increasing parasitic capacitance and vertical crosstalk
Solution Approach 1:
By utilizing the vertical dimension with the semiconductor layer extension, the patent decouples the relationship between horizontal spacing and parasitic capacitance. This allows smaller pixel dimensions for higher resolution while maintaining effective electrical isolation through the vertical stacking approach.
Solution Approach 2:
The semiconductor layer extension acts as an intermediary shielding element between the data line and the driving gate node. This intermediate structure provides electrical isolation that prevents direct capacitive coupling, allowing closer horizontal positioning without increasing crosstalk.
3Stability of the object's composition
If the driving gate-node voltage is increased to compensate for voltage changes caused by parasitic capacitance, then luminance stability is improved, but the risk of OLED damage increases
Solution Approach 1:
The patent extracts the source of voltage instability by physically isolating the driving gate node from the data line through the semiconductor layer extension. This eliminates the parasitic capacitance that causes voltage fluctuations, allowing the driving gate-node voltage to remain stable at safe levels without requiring compensatory voltage increases.
Solution Approach 2:
The semiconductor layer extension provides beforehand cushioning by preemptively blocking the capacitive coupling between the data line and driving gate node. This preventive shielding avoids voltage spikes before they can occur, protecting the OLED from potential damage while maintaining luminance stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces vertical crosstalk, increases the resolution of the OLED display, and improves display quality by more precise control over the gray scale of light emission.
Implementation Method 1
The OLED forms excitons by combining electrons injected from a cathode electrode with holes injected from an anode electrode at the organic emission layer and emits light by allowing the excitons to emit energy
Implementation Method 2
a change in voltage of the data line affects a voltage of a driving gate node of the driving transistor due to a parasitic capacitance formed between a driving gate node and a data line connected to a driving gate electrode of the driving transistor
Data Source
AI summary
An organic light-emitting diode display is disclosed. The display includes a semiconductor layer formed over a substrate, a scan line formed over the semiconductor layer and configured to provide a scan signal, and a light emission control line formed over the semiconductor layer and configured to provide a light emission control signal. The display includes a data line configured to provide a data voltage and a driving voltage line configured to provide a driving voltage, wherein the driving voltage line crosses the scan line and is electrically insulated from the scan line. A switching transistor is electrically connected to the scan line and the data line and includes a switching drain electrode. A driving transistor includes a driving source electrode electrically connected to the switching drain electrode. Any one of the semiconductor layer and the light emission control line includes an extension at least partially overlapping the data line.