OLED Display Panel Data Line Sharing for High Resolution
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Solution Overview
Problem
In the field of OLED displays, the rapid development of high-resolution products increases the requirements for product yield, cost control, and the realization of narrow bezels, but the increased number of pins and lines on circuit boards leads to decreased yield, higher costs, and reduced sub-pixel unit arrangement space.
Innovation Solution
The display panel design reduces the number of data lines by sharing them between sub-pixel units, while maintaining the same number of gate lines, allowing for a larger arrangement area and improved resolution, and incorporates a non-mesh power supply voltage line structure for redundancy and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of sub-pixel units is increased to achieve high resolution, then the display resolution is improved, but the number of pins and lines on circuit boards increases leading to decreased yield and higher costs
Solution Approach 1:
The patent merges the gate line and data line functions into a single integrated line structure. The integrated line serves both as a gate line for scanning signals and as a data line for pixel data transmission, thereby reducing the total number of lines required on the circuit board while maintaining high display resolution
Solution Approach 2:
The integrated line structure performs multiple functions simultaneously - it acts as both a gate line for row scanning and a data line for pixel data transmission. This multi-functionality reduces the number of separate circuit board connections needed, improving yield while supporting high resolution displays
2Manufacturing precision
If the number of sub-pixel units is increased to achieve high resolution, then the display resolution is improved, but the area occupied by lines increases reducing the arrangement space
Solution Approach 1:
The patent combines gate lines and data lines into integrated lines, which reduces the total line area occupied on the substrate. This frees up more space for arranging sub-pixel units, enabling higher display resolution without increasing the overall display area
Solution Approach 2:
The integrated line structure allows for more efficient spatial arrangement by reducing the dimensional footprint of the line network. This creates additional space in the two-dimensional arrangement plane for accommodating more sub-pixel units at higher density
3Manufacturing precision
If the number of data lines is increased to support more sub-pixel units, then the display resolution is improved, but the production cost increases
Solution Approach 1:
The patent merges gate line and data line functions into integrated lines, reducing the total number of lines that need to be manufactured and connected. This simplification reduces production complexity and cost while still supporting high display resolution through efficient signal routing
Data Source
AI summary
A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction.