OLED Display Data Timing for Reduced Frame Drops

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Solution Overview

Problem

In organic light emitting diode (OLED)-type displays, changes in frame length due to delayed input of image data for the next frame lead to difficulties in setting pixel characteristic values, resulting in frame drop phenomena and unnatural screen movements.

Innovation Solution

An electronic device with a display panel, display driver IC, and processor that allows variable setting of operating frequency by adjusting pixel characteristic values to match frame length and transmitting image data during the synchronization signal's high state, reducing frame drop phenomena.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the frame length is changed depending on the point in time when image data of the next frame is input, then the waiting period increases, but it becomes difficult to set pixel characteristic values corresponding to the frame length

Engineering Contradiction:
Improvewaiting periodVSAvoidpixel characteristic value setting
Core Design Contradiction:
Loss of timeVSEase of operation

Solution Approach 1:

The patent applies preliminary action by setting pixel characteristic values in advance based on the fixed frame length before the actual display occurs. The processor determines the frame length based on the fixed refresh rate and pre-configures pixel characteristic values accordingly, rather than attempting to adjust them dynamically after frame length variations occur. This ensures that pixel characteristic values are always available and correctly configured regardless of when image data is actually received.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If image data is delivered at a point in time when the synchronization signal of the next frame is in a high state, then the frame drop phenomenon occurs, but the screen stops during the corresponding frame

Engineering Contradiction:
Improveimage data delivery speedVSAvoidframe delivery accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback by using the synchronization signal as a timing reference to ensure accurate frame delivery. The processor monitors the synchronization signal state and adjusts image data delivery timing accordingly, delivering image data when the synchronization signal is in a low state (indicating the current frame period) rather than when it is in a high state (indicating the next frame period). This feedback mechanism prevents frame drops and maintains display reliability.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If the operating frequency is changed, then the frame length changes, but pixel characteristic values cannot be set to correspond to the frame length

Engineering Contradiction:
Improveoperating frequency adjustmentVSAvoidpixel characteristic value accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by maintaining a fixed frame length parameter regardless of operating frequency variations. The system adjusts other parameters such as refresh rate timing and synchronization signal characteristics to accommodate different operating frequencies while keeping the frame length constant. This allows pixel characteristic values to be set based on the fixed frame length parameter, ensuring accuracy and consistency across different operating frequencies.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12451083B2Electronic device and control method thereof
Publication Date: 2025.10.21 SAMSUNG ELECTRONICS CO LTD
  • US12451083B2 patent drawing
  • US12451083B2 patent drawing
  • US12451083B2 patent drawing

AI summary

An example electronic device includes a display panel configured to display a screen, a display driver IC (DDI) configured to supply a data voltage for displaying the screen to the display panel, and a processor configured to transmit image data for setting the data voltage to the DDI. The DDI is configured to generate a synchronization signal for controlling a time point at which the data voltage is supplied to the display panel, and to deliver the synchronization signal to the processor. The processor is configured to select a time point, at which the image data starts to be transmitted, within a waiting period of the synchronization signal.