OLED Display Module GOA Circuit Layering for Signal Uniformity
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Solution Overview
Problem
The existing Gate Driver on Array (GOA) techniques face issues with non-uniformity in clock signal transmission due to varying pitch between GOA units and their corresponding clock signal wires, leading to resistance loss and parasitic resistance differences.
Innovation Solution
The GOA circuit and clock signal wires are arranged on different layers, with GOA units connected via holes that allow for overlapping projections, ensuring a consistent vertical distance and reducing pitch differences, thereby improving signal uniformity and allowing for a narrower bezel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the GOA circuit and clock signal wires are arranged on the same plane with space spared between them, then the manufacturing process is simplified, but the pitch between GOA units and clock signal wires increases causing resistance loss and signal non-uniformity
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement by placing the GOA circuit and clock signal wires on different layers. This vertical stacking enables the projections to overlap on the substrate, significantly reducing the pitch distance and achieving uniform connection lengths without compromising manufacturing simplicity.
2Manufacturing precision
If the pitch between GOA units and clock signal wires is reduced by overlapping projections, then signal uniformity improves, but the structural complexity increases
Solution Approach 1:
The patent utilizes the third dimension (vertical layering) to achieve projection overlap, which reduces pitch distance while maintaining a relatively simple overall structure. The multi-layer configuration is implemented through standard semiconductor manufacturing techniques, making the increased structural complexity manageable.
3Ease of manufacture
If space is spared between adjacent clock signal wires, then manufacturing is facilitated, but the resistance loss increases affecting clock signal uniformity
Solution Approach 1:
By arranging clock signal wires and GOA circuits on different layers with overlapping projections, the patent reduces the horizontal pitch distance between connection points. This minimizes the length of connecting wires and reduces resistance loss, while the vertical separation between layers maintains manufacturing feasibility.
Data Source
AI summary
A display panel and a display device are provided. The display panel includes a substrate, clock signal wires disposed on the substrate, and a GOA circuit. The GOA circuit includes cascaded GOA units. The GOA circuit and the clock signal wire are arranged on different layers. The GOA units are correspondingly connected to the clock signal wires via holes. A positive projection of the plurality of clock signal wires on the substrate overlaps a positive projection of the GOA circuit on the substrate.