OLED Display Panel Driving Circuit Layout for Smaller Frames
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Solution Overview
Problem
Existing OLED display panels face challenges in optimizing the layout of gate and light-emitting control driving circuits to enhance display performance, particularly in achieving smaller frames and greater screen-to-body ratios for wearable and mobile displays.
Innovation Solution
The display panel incorporates a unique layout where gate and light-emitting control driving circuits are arranged in cascaded multistage units with specific sub-circuits spaced apart by pixel driving circuits, ensuring optimal overlap and connection configurations to minimize overlap with anodes and enhance circuit efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate and light-emitting control driving circuits are arranged in cascaded multistage units with sub-circuits spaced apart by pixel driving circuits, then circuit efficiency is optimized and overlap with anodes is reduced, but device complexity increases
Solution Approach 1:
The gate driving circuit and light-emitting control driving circuit are divided into multiple stages with sub-circuits spaced apart by pixel driving circuits. This segmentation allows each sub-circuit to be independently optimized and reduces interference between adjacent circuits, thereby improving display performance while managing complexity through modular organization.
Solution Approach 2:
The patent utilizes vertical stacking and multi-layer routing to arrange driving circuits in three-dimensional space rather than purely planar layout. By spacing sub-circuits apart in the vertical dimension and using different metal layers for signal routing, the patent reduces overlap with anodes and optimizes circuit efficiency without excessive planar complexity.
2Reliability
If driving circuits are positioned to minimize overlap with anodes, then display quality improves, but the frame size cannot be reduced
Solution Approach 1:
The patent employs vertical stacking and multi-layer architecture to position driving circuits in the vertical dimension above or below the anode layer. This three-dimensional arrangement minimizes planar overlap with anodes, improving display quality while allowing the horizontal frame size to be reduced for smaller wearable and mobile displays.
Solution Approach 2:
The driving circuits are integrated within the pixel structure by nesting them in shared regions or overlapping areas where they can coexist with other pixel components. This nesting approach minimizes the overall frame size while maintaining adequate spacing to prevent harmful overlaps that would degrade display quality.
3Area of stationary object
If cascaded multistage driving units are implemented, then screen-to-body ratio increases, but manufacturing complexity increases
Solution Approach 1:
The cascaded multistage driving units are segmented into standardized modular blocks that can be repeatedly patterned across the display panel. Each stage contains similar sub-circuits that can be manufactured using the same process steps, reducing manufacturing complexity despite the increased number of stages required to achieve high screen-to-body ratios.
Solution Approach 2:
The patent designs universal driving circuit blocks that can serve multiple functions across different stages and pixel types. The same basic circuit architecture is reused throughout the display, allowing standardized manufacturing processes to produce complex multistage configurations without proportionally increasing manufacturing difficulty.
Data Source
AI summary
Provided are a display panel and a manufacturing method thereof, and a display device. The display panel includes: a base substrate including a display area and a peripheral area; a plurality of sub-pixels, each sub-pixel including a light-emitting element and a pixel driving circuit; a plurality of gate lines and light-emitting control lines; a gate driving circuit located at the display area and including cascaded multistage gate driving units, one or more stages include gate driving sub-circuits including a first and a second gate driving sub-circuit spaced apart by pixel driving circuits of a first group of sub-pixels; and a light-emitting control driving circuit located at the display area and including cascaded multistage light-emitting control driving units, one or more stages include light-emitting control driving sub-circuits including a first and a second light-emitting control driving sub-circuit spaced apart by pixel driving circuits of a second group of sub-pixels.