OLED Display Panel Signal Line Sharing for Narrow Bezel Design

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Solution Overview

Problem

In the field of OLED displays, the rapid development of high-resolution products poses challenges for yield, cost control, and the realization of narrow bezels due to increased pin counts on circuit boards, which lead to smaller bonding regions, higher costs, reduced sub-pixel unit areas, and voltage drops causing uneven displays.

Innovation Solution

The display panel design reduces the number of data lines by sharing signal lines, such as gate lines and data lines, and incorporates an auxiliary cathode line to decrease resistance and prevent voltage drops, thereby improving yield, reducing costs, and facilitating narrow bezels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of data lines is increased to support higher resolution, then the resolution is improved, but the bonding region area is reduced and cost increases

Engineering Contradiction:
ImproveresolutionVSAvoidbonding region area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent merges the function of multiple data lines into a single shared data line by implementing a time-division multiplexing scheme where sub-pixel units are driven in different time periods. This allows the same data line to serve multiple sub-pixel units sequentially, reducing the total number of data lines required and thereby increasing the bonding region area.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If the number of data lines is increased to support higher resolution, then the resolution is improved, but production cost increases

Engineering Contradiction:
ImproveresolutionVSAvoidproduction cost
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent combines multiple data line functions into fewer physical lines through time-division multiplexing, reducing the number of pins required on the circuit board. This directly reduces production costs associated with high-pin-count interconnects and complex bonding processes.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If the number of data lines is increased to support higher resolution, then the resolution is improved, but the sub-pixel unit area is reduced

Engineering Contradiction:
ImproveresolutionVSAvoidsub-pixel unit area
Core Design Contradiction:
Measurement precisionVSArea of moving object

Solution Approach 1:

The patent segments the driving process into different time periods, where different groups of sub-pixel units are driven at different times. This temporal segmentation allows fewer data lines to serve more sub-pixel units, enabling larger sub-pixel unit areas while maintaining high resolution through the combined effect of multiple sub-pixels working in sequence.

Inventive Principle:
Principle #1Segmentation

4Area of stationary object

If power supply voltage lines are extended to cover larger areas, then the coverage is improved, but voltage drops increase causing uneven displays

Engineering Contradiction:
Improvecoverage areaVSAvoiddisplay uniformity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent segments the array into multiple sub-pixel unit groups that are driven in different time periods. This allows the use of shorter power supply voltage lines for each group, reducing the length and thereby minimizing voltage drops. Each group receives stable power supply voltage, ensuring display uniformity across the entire panel.

Inventive Principle:
Principle #1Segmentation

5Adaptability or versatility

If the number of pins on circuit board is increased, then the connectivity is improved, but the bonding region area is reduced

Engineering Contradiction:
ImproveconnectivityVSAvoidbonding region area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements multi-functionality in the data lines by allowing a single data line to serve multiple sub-pixel units at different time periods. This universal usage pattern reduces the total number of pins required on the circuit board, thereby increasing the bonding region area while maintaining full connectivity to all sub-pixel units.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11282915B2Display panel and display device
Publication Date: 2022.03.22 HEFEI BOE ZHUOYIN TECH CO LTD
  • US11282915B2 patent drawing
  • US11282915B2 patent drawing
  • US11282915B2 patent drawing

AI summary

A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array, and the array includes N rows and 8M columns. Sub-pixel units in each row are divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, a fifth sub-pixel unit, a sixth sub-pixel unit, a seventh sub-pixel unit and an eighth sub-pixel unit which are sequentially in eight adjacent columns along a first direction.