Drive Circuit for Active Matrix OLED Uniformity
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Solution Overview
Problem
Active matrix organic EL display units face challenges in maintaining uniformity and timing margin due to reduced bezel size, leading to impaired display quality as resolution increases, particularly with the existing methods that fix power line voltage and apply data pulses with three values in each horizontal period.
Innovation Solution
A drive circuit configuration that includes a signal line drive circuit outputting data pulses formed of a signal voltage and one of two fixed voltages based on a picture signal, a scan line drive circuit sequentially outputting selection pulses during a frame period, and a power circuit continuously outputting a constant voltage to power lines, allowing for extended voltage output periods and reduced timing margin risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the voltage of power lines is fixed and data pulse is formed of waveform having three values in 1H, then the scale of power line drive circuit is reduced and bezel size is reduced, but timing margin is lacked and uniformity is impaired due to wiring transient
Solution Approach 1:
The patent applies dynamics by making the power line voltage dynamic rather than fixed. The power line voltage is changed from a fixed waveform to a dynamic waveform that varies according to the display timing and pixel requirements. This allows the system to maintain larger timing margins while adapting the voltage profile to optimize both uniformity and bezel size, resolving the contradiction between reduced bezel size and maintained uniformity
Solution Approach 2:
The patent changes the voltage parameter of the power lines from a fixed three-level waveform to a dynamically adjustable waveform with multiple voltage levels. By changing the voltage parameter timing and magnitude, the system can provide adequate timing margins for high-resolution displays while maintaining reduced bezel size, thus resolving the contradiction between bezel size reduction and uniformity maintenance
2Device complexity
If the voltage of power lines is fixed and data pulse is formed of waveform having three values in 1H, then the scale of power line drive circuit is reduced, but timing margin is lacked due to wiring transient
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed power line voltage waveform to a dynamic waveform that adapts to timing requirements. The dynamic voltage profile allows the system to maintain adequate timing margins despite reduced circuit scale, resolving the contradiction between simplified drive circuit and sufficient timing margin
Solution Approach 2:
The patent applies preliminary action by pre-configuring the power line voltage waveform to account for wiring transient effects before the actual data writing occurs. This preliminary voltage adjustment ensures that timing margins are preserved even with the reduced scale of the power line drive circuit, resolving the contradiction between circuit simplification and timing margin maintenance
Data Source
AI summary
A display unit includes: a display panel; and a drive circuit. The display panel includes pixels arranged in a matrix, signal lines configured to supply a data pulse to the respective pixels, scan lines configured to supply a selection pulse to the respective pixels, the selection pulse selecting the respective pixels for each row, and power lines configured to supply power to the respective pixels. The drive circuit includes a signal line drive circuit configured to output the data pulse to each of the signal lines, a scan line drive circuit configured to sequentially output the selection pulse to each of the scan lines, and a power circuit configured to continuously output a constant voltage to the power lines. The data pulse is formed of a signal voltage and one of a first fixed voltage and a second fixed voltage, the signal voltage based on a picture signal.