OLED Driver Buffer Circuit Parasitic Capacitance Reduction
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Solution Overview
Problem
The existing organic light emitting display devices face instability in signal output due to parasitic capacitance generated from buffer circuits in the drivers, which increases with the size of the output terminals, hindering the scalability of the panels.
Innovation Solution
The implementation of a metal layer for Electro-Static Discharge (ESD) shielding on the upper surface of drivers, with the metal layer formed as an anode or cathode electrode, and extending the source or drain electrode of transistors to minimize the overlapping region with the gate electrode, thereby reducing parasitic capacitance in the buffer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the output terminal size is increased to handle larger panel sizes, then the driving capability is improved, but the parasitic capacitance increases causing signal output instability
Solution Approach 1:
The patent extracts and removes the harmful overlapping region between the gate electrode and metal layer. By defining the metal layer formation region to exclude the upper region of the gate electrode, the parasitic capacitance is eliminated while maintaining the buffer circuit's driving capability for large panel sizes.
Solution Approach 2:
The patent applies local quality by creating a non-uniform metal layer distribution. The metal layer is formed in regions needing ESD protection and driver functionality, but intentionally omitted from the gate electrode upper region where it would create parasitic capacitance. This localized modification resolves the contradiction between driving capability and signal stability.
2Area of stationary object
If the buffer circuit size is increased to drive larger panels, then the output capability is improved, but the parasitic capacitance increases hindering panel scalability
Solution Approach 1:
The patent extracts the harmful parasitic capacitance by preventing the formation of overlapping regions between the gate electrode and metal layer. This allows the buffer circuit to be scaled up for larger panels without the detrimental effect of increased parasitic capacitance, thus enabling panel scalability.
Solution Approach 2:
The patent implements local quality by selectively forming the metal layer only in regions where it provides benefit (ESD protection, driver functionality) while avoiding the gate electrode upper region. This localized approach enables the buffer circuit to support larger panel areas without generating harmful parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures stable output from the drivers by minimizing parasitic capacitance, allowing for larger panel sizes while maintaining signal integrity.
Implementation Method 1
a metal layer for shielding an Electro-Static Discharge (ESD) formed on an upper surface of each driver
Implementation Method 2
an organic light emitting diode (OLED) generating light by recombination of an electron and a hole
Data Source
AI summary
An organic light emitting display device comprising: a data driver supplying data signals to data output lines; a scan driver supplying scan signals sequentially to scan output lines; a light emitting control line driver supplying light emitting control signals to light emitting control output lines; and a pixel unit including a plurality of pixels connected to the output lines of each driver, at least one driver having a buffer circuit disposed at each output line. Each buffer circuit comprises a transistor having a gate layer, source and drain layers and a metal layer for shielding Electro-Static Discharge (ESD), wherein the metal layer is formed over the gate layer when the gate layer is overlapped by one of the source or a drain electrodes, or the metal layer is formed to not overlap the gate layer when the gate layer is not overlapped by the source or a drain electrodes.