OLED Data Driver DAC with Intermediate Gray Precharge
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Solution Overview
Problem
The driving speed of conventional organic light emitting displays is limited due to the time required for voltage division using resistors, which results in insufficient charging of pixels within the required horizontal period, leading to low driving speed and potential gray scale precision issues.
Innovation Solution
A data driver circuit arrangement that includes a first digital-to-analog converter for selecting reference voltages based on upper bits and a second digital-to-analog converter for dividing these voltages, with a capacitor to supply an intermediate gray scale voltage before the data signal, allowing faster charging and improved precision by bypassing voltage dividers for reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage division using resistors is used to generate data signals, then gray scale precision is achieved, but driving speed decreases due to the time required for voltage division
Solution Approach 1:
The patent applies preliminary action by pre-charging the pixel electrodes to an intermediate gray scale voltage before the final data signal is applied. This intermediate charging step prepares the pixels in advance, allowing the subsequent voltage division process to complete faster within the horizontal period, thus resolving the contradiction between precision and speed.
Solution Approach 2:
The patent extracts the time-consuming voltage division operation from the critical data signal path by performing it in parallel with the intermediate gray scale voltage charging. The voltage dividers continue to operate and provide precise voltage division, but this process is no longer the bottleneck since the pixels are already charged to the intermediate level.
2Manufacturing precision
If voltage division using resistors is used to generate data signals, then gray scale levels are accurately generated, but pixel charging is insufficient within the horizontal period
Solution Approach 1:
The intermediate gray scale voltage is applied in advance to charge the pixels partially before the final data signal. This preliminary charging ensures that pixels receive sufficient charge within the horizontal period, while the voltage dividers continue to provide accurate gray scale level generation without time pressure.
Solution Approach 2:
The patent segments the voltage application process into two phases: an intermediate gray scale voltage phase for rapid preliminary charging, and a final data signal phase for precise gray scale level establishment. This segmentation allows each phase to optimize for its specific function, ensuring both charging completeness and accuracy.
3Device complexity
If conventional data signal generation is used, then circuit simplicity is maintained, but driving speed and response time are insufficient
Solution Approach 1:
The patent merges the intermediate gray scale voltage generation circuit with the existing voltage divider circuit. The same voltage dividers that generate precise gray scale levels are used to generate the intermediate gray scale voltage, eliminating the need for separate circuitry and maintaining circuit simplicity while achieving faster response time.
Solution Approach 2:
The voltage divider circuit is given multi-functionality by using it to generate both the intermediate gray scale voltage and the final precise data signals. This universal use of the voltage dividers avoids adding complex dedicated circuitry for intermediate charging, maintaining simplicity while improving performance.
Data Source
AI summary
A data driver, including a first digital-to-analog converter configured to select two reference voltages of a plurality of reference voltages depending on upper bits of data, and a second digital-to-analog converter configured to divide the two reference voltages into a plurality of voltages and supply any one voltage of the two reference voltages and the divided voltages to an output terminal as a data signal depending on lower bits of the data, wherein the second digital-to-analog converter is configured to supply an intermediate gray scale voltage to the output terminal prior to supplying the data signal, the intermediate gray scale voltage having a voltage between the two reference voltages.