OLED Dual Gate Transistor Nested Electrode Design

The patent implements a nested dual gate structure where a first gate electrode and a second gate electrode are positioned at different vertical levels within the same transistor channel region. The first gate electrode is formed in a lower layer while the second gate electrode is formed in an upper layer, creating a nested configuration that reduces off-leakage current through enhanced electric field control without proportionally increasing device footprint

The patent transitions from a planar single gate structure to a three-dimensional dual gate structure by adding vertical layering. The first and second gate electrodes are disposed at different heights (Z-dimension) above the semiconductor channel, utilizing the vertical dimension to increase gate control effectiveness without significantly expanding the horizontal device area, thereby addressing the complexity issue

The gate electrode system is segmented into distinct first and second gate electrodes formed in separate manufacturing layers. The first gate electrode is formed in an initial gate layer while the second gate electrode is formed in a subsequent gate layer, allowing independent formation and alignment processes for each segment, which manages manufacturing precision requirements through modular fabrication

Gate insulating layers serve as intermediary structures between the first and second gate electrodes. These insulating layers provide physical separation and alignment references, acting as mediators that facilitate precise positioning of the second gate electrode relative to the first gate electrode during the manufacturing process, thereby managing alignment precision requirements