OLED Electrode Opening Layout for Low-Coupling Scan Clock Lines
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Solution Overview
Problem
As display devices increase in size and resolution, the integration of driving circuits and signal lines increases, leading to higher power consumption and potential reliability issues.
Innovation Solution
The display device incorporates a design with a base layer, circuit layer, and light-emitting elements featuring a second electrode with defined openings overlapping scan clock lines, sub-electrodes connected by a connection electrode, and insulation films with separators, reducing capacitive coupling and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of signal lines and connection electrodes is increased to support higher size and resolution, then the display capability is improved, but the power consumption increases and reliability decreases
Solution Approach 1:
The patent extracts the harmful capacitive coupling effect by introducing openings in the second electrode that expose the scan clock line. This removes the parasitic capacitance between the second electrode and scan clock line, thereby reducing power consumption while maintaining high resolution display capabilities through increased signal lines and connection electrodes
2Measurement precision
If the number of signal lines and connection electrodes is increased to support higher size and resolution, then the display capability is improved, but reliability decreases
Solution Approach 1:
The patent extracts the reliability issue caused by capacitive coupling by exposing the scan clock line through openings in the second electrode. This eliminates the parasitic capacitance that could cause signal interference and malfunction, thereby improving device reliability while supporting higher resolution through increased signal lines
Solution Approach 2:
The patent introduces an intermediary structure where the opening in the second electrode acts as a mediator to prevent direct capacitive coupling between the second electrode and scan clock line. This intermediary design reduces signal interference and improves reliability while maintaining the necessary number of connection electrodes for high resolution
3Ease of manufacture
If the second electrode is made as a continuous layer, then the manufacturing process is simpler, but capacitive coupling with scan clock lines increases leading to higher power consumption
Solution Approach 1:
The patent segments the second electrode by introducing openings that expose the scan clock line. This segmentation creates discontinuities in the second electrode layer, eliminating capacitive coupling with the scan clock line while maintaining ease of manufacture through standard thin-film deposition processes with additional patterning steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption and enhances reliability by minimizing capacitive coupling between electrodes and signal lines, improving the overall performance of the display device.
Implementation Method 1
reduces capacitive coupling and power consumption
Data Source
AI summary
A display device includes a base layer in which a display region and a non-display region adjacent to the display region are defined; a circuit layer including a scan clock line in the non-display region and extending in a first direction, and a scan driver connected to the scan clock line; and a light-emitting element on the circuit layer, and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer, wherein a first opening overlapping the scan clock line is defined in the second electrode.