OLED Encapsulation Design Mitigating GIP Capacitive Coupling
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Solution Overview
Problem
Active matrix OLED display panels face challenges in reducing capacitive coupling between the gate driver in panel (GIP) clock signals and the negative supply electrode (VSSEL) contact region, while also requiring effective encapsulation to protect against moisture and ensuring structural integrity, particularly during handling and scoring.
Innovation Solution
The display panel design includes a first metal layer spanning the VSSEL contact region and the pixel area region, with an array of anode contacts, and a VSSEL contact layer in the VSSEL contact region that does not overlap the GIP clock region, along with a cathode layer confined to the pixel area region, using overlapping inorganic layers to create a moisture barrier and provide structural integrity by avoiding deep trenches near the GIP region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the VSSEL contact region is positioned adjacent to the GIP region, then the display panel can achieve a narrow border design, but capacitive coupling between the GIP clock signals and the VSSEL contact region increases
Solution Approach 1:
The patent extracts the VSSEL contact region from direct adjacency to the GIP region by introducing an intermediate buffer region. This separation removes the harmful capacitive coupling effect while maintaining the narrow border design goal, as the buffer region acts as an isolation zone between the two functional areas.
Solution Approach 2:
The patent introduces a buffer region as an intermediary element between the GIP region and the VSSEL contact region. This intermediary structure reduces capacitive coupling by providing electrical isolation, allowing the VSSEL contact to be positioned closer to the GIP region than direct adjacency would permit without excessive coupling.
2Object-affected harmful factors
If deep trenches are used for encapsulation, then moisture protection is improved, but structural integrity deteriorates due to potential cracking during handling and scoring
Solution Approach 1:
The patent applies different trench depths at different locations: shallow trenches are used in regions prone to cracking (near edges and scribe lines) to maintain structural integrity, while deeper trenches are used in protected regions to provide enhanced moisture protection. This localized differentiation resolves the contradiction between moisture protection and structural strength.
Solution Approach 2:
Instead of using uniformly deep trenches throughout the display panel, the patent employs partial deepening only where necessary for moisture protection while maintaining shallower trenches elsewhere. This partial action approach provides sufficient moisture barrier functionality without the excessive structural weakening that would result from uniform deep trenching.
3Reliability
If the cathode layer is extended to the VSSEL contact region, then electrical contact is improved, but the risk of cracking and moisture ingress increases near the panel edges
Solution Approach 1:
The patent segments the cathode layer into distinct regions: a continuous cathode layer in the pixel area for optimal electrical contact, and a discontinuous or absent cathode layer at the edges and in the buffer region where cracking risk is high. This segmentation maintains electrical functionality where needed while avoiding the harmful effects of edge-proximity cathode structures.
Data Source
AI summary
Display panels and encapsulation structures are described for OLED display panels, in particular. In an embodiment, a display panel includes a gate driver in panel (GIP) region, a GIP clock region within the GIP region, a pixel area region, and a VSSEL contact region laterally between an outer edge of the GIP region and the pixel area region. In some embodiments, structures are described in which capacitive coupling with the GIP clock region can be mitigated, and overlapping inorganic layers form a barrier to moisture outside of the pixel area region.