OLED Gate Driving Circuit Layout With Shared Clock Lines
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Solution Overview
Problem
Existing display apparatuses face high power consumption due to the need for multiple clock lines to supply gate signals to the gate driving circuit.
Innovation Solution
The display apparatus reduces power consumption by sharing a single clock line between two gate driving circuits, which output gate signals to multiple rows of pixels, and arranging these circuits on different layers with insulating layers in between, while using transistors symmetrically connected to the clock lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock lines are used to supply gate signals to the gate driving circuit, then the gate driving circuit can operate reliably, but power consumption increases
Solution Approach 1:
The patent combines multiple clock lines into a single shared clock line that supplies clock signals to both third and fourth driving circuits. This merging reduces the total number of clock lines from multiple separate lines to one common line, thereby reducing power consumption while maintaining reliable operation of the gate driving circuit through proper signal distribution to both circuits.
Solution Approach 2:
The single clock line serves multiple functions by simultaneously supplying clock signals to both the third driving circuit (which outputs third gate signals) and the fourth driving circuit (which outputs fourth gate signals). This multi-functional use of the clock line eliminates the need for separate dedicated clock lines for each driving circuit, reducing overall power consumption.
2Use of energy by moving object
If a single clock line is shared between two gate driving circuits, then power consumption is reduced, but signal interference may occur
Solution Approach 1:
The patent resolves signal interference by arranging the third and fourth driving circuits on different layers (vertical dimension) rather than placing them adjacent to each other on the same layer. This spatial separation in the vertical dimension allows both circuits to share the same clock line without experiencing signal interference, as the insulating layers between layers electrically isolate the two circuits while still allowing the clock signal to be distributed to both.
3Reliability
If multiple clock lines are used, then signal integrity is maintained, but device complexity increases
Solution Approach 1:
The patent merges multiple separate clock lines into a single shared clock line that distributes clock signals to both third and fourth driving circuits. This reduction from multiple lines to one line simplifies the overall device structure and reduces complexity, while signal integrity is maintained through proper timing control and the use of insulating layers to prevent interference.
Data Source
AI summary
A display apparatus includes: pixels arranged in a display area, and a driving circuit arranged in a peripheral area outside the display area and for outputting a gate signal to the pixels. Each of the pixels includes: a driving transistor for outputting a driving current corresponding to a data signal, a light-emitting element for emitting light with luminance corresponding to the driving current, a first transistor diode-connecting the driving transistor, a second transistor for transmitting a first initialization voltage to a gate of the driving transistor, a third transistor for transmitting a driving voltage to the driving transistor, and a fourth transistor for transmitting a second initialization voltage to a pixel electrode of the light-emitting element. A third driving circuit for outputting a third gate signal to the third transistor and a fourth driving circuit for outputting a fourth gate signal to the fourth transistor share a clock line.