OLED Display Gate Control for Low-Refresh Insulating Layer Protection
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Solution Overview
Problem
OLED display devices experience deterioration and reliability issues due to bending cracks in the insulating layer of signal lines when driven at low refresh rates, primarily caused by the consistent application of a logic low voltage during the anode reset subframe, leading to ion attraction and layer degradation.
Innovation Solution
Implementing a gate control signal that alternates between logic high and low voltages during the anode reset subframe, with a longer logic high voltage period, to minimize insulating layer deterioration and prevent bending cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the OLED display device is driven with a low refresh rate (e.g., 1 Hz in standby mode), then power consumption is reduced, but the gate control signal is maintained at logic low voltage during the anode reset subframe, causing positive ion attraction and insulating layer deterioration
Solution Approach 1:
The gate control signal is modified to periodically switch between logic high voltage and logic low voltage during the anode reset subframe instead of maintaining a constant logic low voltage. This periodic switching prevents continuous positive ion attraction while still allowing the display to operate in low refresh rate standby mode, thus reducing insulating layer deterioration without sacrificing power savings
Solution Approach 2:
The voltage level parameter of the gate control signal is dynamically changed during the anode reset subframe. Instead of maintaining a fixed logic low voltage, the signal alternates between logic high and logic low states, changing the electrical parameter to prevent ion accumulation and protect the insulating layer while maintaining low power operation
2Productivity
If the gate control signal is maintained at logic low voltage during the anode reset subframe, then the display can operate in low refresh rate mode, but the signal line consistently attracts positive ions causing bending cracks
Solution Approach 1:
The gate control signal implements periodic voltage switching during the anode reset subframe, alternating between logic high and logic low states. This periodic action prevents continuous ion attraction that would cause bending cracks, while still enabling the display to maintain flexible refresh rate operation including low refresh rate standby mode
3Reliability
If the gate control signal alternates between logic high and low voltages during the anode reset subframe, then insulating layer deterioration is reduced, but the signal line experiences repeated voltage transitions
Solution Approach 1:
The gate control signal uses periodic voltage switching during the anode reset subframe to protect the insulating layer. While this introduces voltage transitions, the pattern is systematic and time-defined, making the complexity manageable through synchronized control that aligns with the display's existing refresh cycle structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of OLED display devices by reducing insulating layer degradation and preventing bending cracks, thereby improving overall device performance.
Implementation Method 1
since a signal line transmitting the gate control signal consistently attracts a positive ion, an insulating layer on the signal line is deteriorated
Data Source
AI summary
A display device includes: a timing controlling unit configured to generate an image data, a data control signal and a gate control signal; a data driving unit configured to generate a data signal using the image data and the data control signal; a gate driving unit configured to generate a gate signal using the gate control signal; and a display panel configured to display an image using the data signal and the gate signal, wherein a start signal of the gate control signal has one pulse between a logic high voltage and a logic low voltage during a refresh subframe where the data signal and the gate signal are supplied and has a plurality of pulses between the logic high voltage and the logic low voltage during an anode reset subframe where supply of the data signal and the gate signal is stopped.