OLED Gate Driver Circuitry Using True and Complementary Clocks
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Solution Overview
Problem
Conventional gate driver circuits in OLED displays are inefficient and consume substantial power due to reliance on a single clock edge for triggering, leading to high power consumption.
Innovation Solution
Implementing gate driver circuitry that utilizes both rising and falling edges of clock signals, coupled with inverted clock signals, to reduce the required clock frequency by half and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If gate driver circuits rely on a single clock edge for triggering, then the circuit design is simple, but power consumption is high
Solution Approach 1:
The gate driver circuit utilizes both rising and falling edges of the clock signal to trigger operations, effectively doubling the utilization of each clock cycle. This periodic action on both edges reduces the required clock frequency by half, thereby reducing dynamic power consumption proportionally while maintaining the same data throughput.
Solution Approach 2:
The circuit dynamically responds to both rising and falling edges of the clock signal rather than being static in responding to only one edge. This dynamic approach allows the circuit to perform operations during both clock transitions, improving efficiency without requiring a fundamentally different circuit architecture.
2Use of energy by moving object
If gate driver circuits use both rising and falling edges of clock signals, then power consumption is reduced by approximately 50%, but the circuit complexity increases due to additional inverters and signal lines
Solution Approach 1:
The clock signal distribution is segmented into separate paths: one path provides the original clock signal to circuits that need rising edge triggering, while another path uses an inverter to provide the inverted clock signal for falling edge triggering. This segmentation allows independent optimization of different circuit stages.
Solution Approach 2:
An inverter is introduced as an intermediary component to generate the inverted clock signal from the original clock signal. This intermediary enables the system to access both rising and falling edges without fundamentally altering the clock generation architecture, adding minimal complexity while achieving the dual-edge triggering benefit.
3Speed
If gate driver circuits use inverted clock signals, then the required clock frequency is reduced by half, but additional clock signal lines and inverters are required
Solution Approach 1:
By utilizing both rising and falling edges of the clock signal in a periodic manner, the effective data throughput per unit time is doubled at the same clock frequency, or equivalently, the required clock frequency is halved for the same throughput. This periodic utilization of both edges maximizes the efficiency of each clock cycle.
Solution Approach 2:
The clock signal infrastructure is designed to serve multiple functions: the original clock signal line serves circuits requiring rising edge triggering, while the inverted clock signal line serves circuits requiring falling edge triggering. This multi-functionality allows the system to achieve dual-edge operation without proportionally increasing the clock distribution network complexity.
Data Source
AI summary
A display may include an array of pixels that receive row control signals from gate driver circuitry. The gate driver circuitry can include a chain of gate drivers configured to receive one or more clock signals. The gate driver circuitry can further include inverters configured to invert the one or more clock signals to generate inverted clock signals. The clock signals and the inverted clock signals can be conveyed to the chain of gate drivers. Falling edges of the clock signals and the inverted clock signals can be used to trigger assertions and deassertions of the row control signals. Operated in this way, the power consumption of the gate driver circuitry can be reduced.