OLED Pixel Gate Driver Using Shared Scan Signals for Initialization
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Solution Overview
Problem
Existing display devices suffer from the technical field of display devices and electronic devices, the technical problem of inefficient hysteresis improvement and initialization voltage input operations in organic light emitting display devices, leading to complex circuit structures and increased size.
Innovation Solution
A display device with a dual or triple-gate formation structure for transistors in pixel circuits, utilizing a gate driver to supply gate scan signals for initializing and compensating transistors, reducing the need for additional control signals and input lines, thereby simplifying the gate driver circuit and reducing its size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate control signals and input lines are added for hysteresis improvement and initialization voltage input, then the hysteresis improvement and initialization operations can be performed, but the circuit structure becomes complex and the gate driver size increases
Solution Approach 1:
The gate driver is designed to perform multiple functions using existing structures. The gate scan signals are reused for both hysteresis improvement and initialization voltage input operations, allowing the same circuit elements to serve multiple purposes without requiring separate dedicated control signals or input lines.
Solution Approach 2:
The patent combines the hysteresis improvement operation and initialization voltage input operation into a unified process. By merging these functions and using the existing gate scan signal lines for both purposes, the circuit structure is simplified and the gate driver size is reduced while maintaining both operational capabilities.
2Reliability
If separate control signals and input lines are added for hysteresis improvement and initialization voltage input, then the initialization voltage input operation can be performed, but the gate driver size and placement area increase
Solution Approach 1:
The gate driver circuit elements are designed to perform multiple functions. The same gate scan signal lines and control structures are utilized for both initialization voltage input and hysteresis improvement operations, eliminating the need for separate dedicated components and reducing the overall placement area.
Solution Approach 2:
The patent merges the initialization voltage input function with the existing gate driver structure. By combining this function with the hysteresis improvement operation and using shared circuit elements, the gate driver placement area is minimized while ensuring reliable initialization voltage input capability.
3Reliability
If dual or triple-gate formation structure is implemented, then the transistor performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The transistor gate structure is divided into multiple gates (dual or triple-gate configuration). This segmentation allows each gate to be controlled independently or in coordination, improving transistor performance through better electrostatic control and threshold voltage modulation, while the manufacturing process can be adapted by forming these gates in sequence or using specialized deposition techniques.
Data Source
AI summary
A display device includes: a display panel in which pixels are arranged in a display area to display an image; and a gate driver configured to supply gate scan signals to the pixels on a horizontal line-by-horizontal line basis, wherein from among the pixels, pixels that are on a same horizontal line along each gate line are configured to initialize a gate electrode, a first electrode and a second electrode of a first transistor to an emission initialization voltage in response to a previous gate initialization signal supplied to pixels of a previous horizontal line and a current compensation gate signal from among the gate scan signals in a first period, to initialize the second electrode of the first transistor to an initialization voltage in response to a current gate initialization signal and the current compensation gate signal from among the gate scan signals in a second period.