OLED Display Gate Voltage Circuit Timing for Mura Compensation
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Solution Overview
Problem
The mura phenomenon in OLED displays, caused by non-uniform electrical parameters of thin film transistors in different driving circuits, results in uneven luminance across the screen, which conventional compensation circuits cannot fully eliminate, especially at high frame scanning frequencies.
Innovation Solution
A display apparatus with a gate voltage generation circuit that generates scan signals to control write and reset circuits in pixel circuit rows, where the timing of scan signals is adjusted to ensure that each pixel circuit has sufficient valid write phases, allowing the voltage at a storage capacitor to be adjusted to a specific voltage that compensates for threshold voltage differences, thereby eliminating luminance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional compensation circuits (6T1C, 7T1C, or 8T1C) are used to eliminate mura phenomenon, then threshold voltage impact can be compensated, but at high frame scanning frequencies the write phase becomes too short to fully eliminate the mura phenomenon
Solution Approach 1:
The patent applies dynamics by making the scan signal timing flexible and adjustable. Specifically, the timing of scan signals is adjusted dynamically to ensure that even at high frame scanning frequencies, the write phase duration is sufficient for voltage compensation. This allows the system to adapt to different scanning frequencies while maintaining effective mura phenomenon elimination.
Solution Approach 2:
The patent changes the timing parameter of scan signals to resolve the contradiction. By adjusting when scan signals are applied to different pixel circuit rows, the patent ensures that the write phase has adequate duration for voltage compensation even at high scanning frequencies. This parameter adjustment allows the compensation function to work effectively regardless of the frame scanning frequency.
2Productivity
If the write phase is shortened due to high frame scanning frequency, then higher scanning speed is achieved, but the impact of threshold voltage on drive current cannot be eliminated
Solution Approach 1:
The patent applies preliminary action by adjusting the timing of scan signals in advance to ensure that the write phase has sufficient duration for voltage compensation. By carefully controlling when scan signals are applied to different pixel circuit rows, the patent ensures that the voltage compensation process can complete adequately even at high scanning frequencies, thus maintaining manufacturing precision.
Solution Approach 2:
The patent uses dynamics to make the scan signal timing adaptable. The timing is dynamically adjusted to optimize the write phase duration, allowing the system to maintain voltage compensation precision while operating at high frame scanning frequencies. This dynamic timing adjustment resolves the conflict between productivity and manufacturing precision.
3Ease of operation
If scan signals are applied to all pixel circuit rows simultaneously, then operation simplicity is maintained, but the write phase duration is insufficient for effective voltage compensation
Solution Approach 1:
The patent applies segmentation by dividing the pixel circuit rows into different groups that receive scan signals at different times. Instead of applying scan signals to all rows simultaneously, the patent segments the rows and applies timing offsets, which extends the write phase duration for compensation while maintaining relatively simple control through systematic timing adjustments.
Solution Approach 2:
The patent uses dynamics to adjust scan signal timing to optimize the write phase duration. By dynamically controlling when different pixel circuit rows receive scan signals, the patent extends the effective write phase duration for voltage compensation while keeping the control mechanism relatively simple through systematic timing offsets.
Data Source
AI summary
A display apparatus including a plurality of pixel circuit rows, where each pixel circuit row includes a plurality of pixel circuits, and each pixel circuit includes a light emitting component and a driving circuit. A gate voltage generation circuit generates a plurality of scan signals. A first scan signal and a second scan signal respectively control write circuits in driving circuits in a first pixel circuit row and a second pixel circuit row. The write circuit adjusts, based on a data voltage for controlling luminance of a light emitting component, a voltage at one end of a storage capacitor to a first voltage. The first scan signal further controls a reset circuit in a driving circuit in a second pixel circuit row, and the reset circuit resets the voltage at one end of the storage capacitor to a second voltage based on a reference voltage.