OLED Display Panel Groove Segmentation for Brightness Uniformity

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Solution Overview

Problem

In large OLED display panels, the resistance of the cathode material leads to voltage drop and decreased display brightness due to its inherent resistance value, causing issues with brightness uniformity and reliability.

Innovation Solution

A display panel design featuring a conductive layer with a groove that divides the gate layer into disconnected portions, reducing the height difference between the auxiliary electrode layer and the substrate, and using multiple insulating layers to prevent short circuits, along with a manufacturing method that forms these layers to ensure uniformity and prevent defective etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the OLED panel size is increased, then the display area is improved, but the voltage drop increases causing brightness decrease

Engineering Contradiction:
Improvedisplay areaVSAvoidbrightness
Core Design Contradiction:
Area of stationary objectVSIllumination intensity

Solution Approach 1:

The gate layer is divided into multiple disconnected portions by forming grooves that extend from the front surface toward the substrate. This segmentation reduces the height difference between the auxiliary electrode layer and substrate, thereby reducing voltage drop and improving brightness uniformity across large display areas

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solution introduces a vertical dimension modification by creating grooves that change the height profile of the gate layer. This dimensional change allows the auxiliary electrode layer to be positioned closer to the substrate in specific regions, reducing the effective path length for current flow and minimizing voltage drop

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the gate layer thickness is increased, then the gate control capability is improved, but the height difference between auxiliary electrode layer and substrate increases

Engineering Contradiction:
Improvegate control capabilityVSAvoidheight difference
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

By segmenting the gate layer into disconnected portions through grooves, the effective height difference is reduced while maintaining sufficient gate control capability in each segmented region. The gate layer thickness can be optimized for control capability without proportionally increasing the overall height difference

Inventive Principle:
Principle #1Segmentation

3Loss of energy

If the conductive layer resistance is reduced, then the voltage drop is minimized, but the material selection and manufacturing complexity increase

Engineering Contradiction:
Improvevoltage dropVSAvoidmanufacturing complexity
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The groove structure segments the conductive path, allowing the use of standard conductive layer materials without requiring extremely low-resistance materials. The segmented structure reduces the effective path length and resistance impact while maintaining manufacturing feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The groove structure acts as an intermediary that modifies the electrical path without requiring changes to the conductive layer material properties. This intermediate structural modification achieves voltage drop reduction while keeping material selection and manufacturing processes relatively simple

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10916615B1Display device, display panel and manufacturing method thereof
Publication Date: 2021.02.09 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US10916615B1 patent drawing
  • US10916615B1 patent drawing

AI summary

A display panel includes a substrate; a conductive layer disposed on the substrate; a gate insulating layer disposed on the conductive layer; a gate layer disposed on the gate insulating layer, wherein the gate layer has a thickness larger than a thickness of the conductive layer; a groove extending toward the substrate and punching through the gate layer, orthographic projections of the groove and the conductive layer on the substrate overlapping, and gate layers separated on two sides of the groove being connected to the conductive layer; an interlayer dielectric layer disposed on a side of the gate layer away from the substrate and covering the conductive layer and filling the groove; and an auxiliary electrode layer disposed on the interlayer dielectric layer, wherein the orthographic projections of the auxiliary electrode layer and the gate layer on substrate do not overlap, and the orthographic projections of the auxiliary electrode layer and the groove on the substrate overlap.