OLED Display Insulating Layer Crosstalk Reduction
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Solution Overview
Problem
High-resolution organic light emitting diode (OLED) displays face challenges in minimizing crosstalk due to parasitic capacitance, which affects the driving gate voltage and luminance, especially as pixel size decreases with increasing resolution.
Innovation Solution
The OLED display incorporates a substrate with a semiconductor structure including transistors and doping regions, with a gate insulating layer and interlayer insulating layer configuration that minimizes parasitic capacitance by positioning an organic layer between signal lines, using contact holes with specific side wall configurations to reduce kickback voltage and expand the driving gate-source voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the interval between the data line and the driving gate node is increased to minimize crosstalk, then the parasitic capacitance is reduced, but the pixel size cannot be reduced further due to facility specification limitations and photolithography process capability
Solution Approach 1:
The patent applies local quality by forming an organic insulating layer specifically in the region between the data line and the driving gate node, rather than uniformly across the entire pixel. This localized approach minimizes parasitic capacitance in the critical crosstalk area while maintaining compact pixel dimensions. The organic layer is positioned precisely where needed to reduce capacitance without requiring overall pixel enlargement.
2Measurement precision
If the pixel size is reduced to increase resolution, then the display resolution is improved, but the interval between the data line and the driving gate node cannot be sufficiently increased, leading to increased crosstalk
Solution Approach 1:
The patent implements local quality by selectively placing an organic insulating layer only in the region between the data line and the driving gate node within the compact pixel structure. This localized insulation reduces parasitic capacitance and crosstalk effects even though the overall pixel size remains small for high resolution. The organic layer is positioned precisely in the critical area where crosstalk occurs, allowing high resolution display without sacrificing signal integrity.
3Device complexity
If a conventional insulating layer is used between signal lines, then the structure is simple, but the parasitic capacitance is not sufficiently minimized due to the fixed dielectric properties of inorganic materials
Solution Approach 1:
The patent applies parameter changes by replacing the conventional inorganic insulating layer with an organic insulating layer in the specific region between the data line and the driving gate node. The organic material provides different dielectric properties (lower dielectric constant) compared to traditional inorganic materials, which directly reduces the parasitic capacitance in this critical area. This material substitution effectively minimizes crosstalk without significantly complicating the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes crosstalk, enhances the driving range of the driving gate-source voltage, and increases the resolution and display quality of the OLED by controlling gray levels of light emission.
Implementation Method 1
an organic emission layer disposed therebetween and forms excitons by combining electrons injected from one electrode with holes injected from another electrode at the organic emission layer, and emits light by allowing the excitons to emit energy
Data Source
AI summary
An organic light emitting diode display includes a substrate, a semiconductor disposed on the substrate that includes a channel for each of a plurality of transistors and doping regions formed at both sides of each channel; a gate insulating layer disposed on the semiconductor that includes an insulating layer opening through which the doping regions of two different transistors are exposed; a gate electrode disposed on the gate insulating layer that overlaps each channel; an interlayer insulating layer disposed on the gate electrode that includes a first and second contact holes through which the doping regions exposed within the insulating layer opening are each exposed; and data wirings disposed on the interlayer insulating layer that are each connected to the doping regions. The interlayer insulating layer includes an organic layer, and the first and second contact holes each include a first side wall positioned within the insulating layer opening.