Insulating Layer Etching Sequence for OLED Contact Openings
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Solution Overview
Problem
In the manufacturing of OLED display devices, the process of etching stacked insulating layers often results in incomplete etching or overetching, leading to defects and damage to underlying layers, which hinders the achievement of high resolution and reliable connections between transistors.
Innovation Solution
A method involving sequential etching steps with specific etching gases and selection ratios is employed to uniformly etch the insulating layers, ensuring that each layer is properly exposed and removed without damaging underlying structures, using gases like pentafluoroethane, argon, hydrogen, chlorine, and carbon tetrafluoride to control the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching depth is increased to form openings through stacked insulating layers for high resolution, then the connection between transistors is improved, but defects occur during the etching process such as incomplete etching or overetching
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching steps (first etching, second etching, third etching) with different etching gases and parameters. Each step targets specific insulating layers with controlled depth, preventing the defects that occur in deep single-step etching while achieving the necessary total etching depth for high-resolution transistor connections.
Solution Approach 2:
The patent changes etching parameters including gas composition (CF4, SF6, C4F8, H2, Ar), power, pressure, and temperature across different etching steps. By adjusting these parameters, the etching rate and selectivity are optimized for each specific insulating layer, enabling precise depth control and preventing both incomplete etching and overetching.
2Manufacturing precision
If multiple insulating layers are etched to achieve high resolution, then the number of layers is increased, but the etching process becomes more complex and prone to defects
Solution Approach 1:
The patent segments the etching process into distinct steps, each targeting specific insulating layers (first interlayer insulating layer, second interlayer insulating layer, third interlayer insulating layer) with dedicated etching gases and parameters. This segmentation simplifies the control of each individual etching step while achieving the complex overall goal of forming openings through multiple layers.
Solution Approach 2:
The patent performs preliminary etching steps to expose specific layers (e.g., exposing the active layer by etching the first and second interlayer insulating layers) before proceeding to subsequent etching steps. This preliminary action prepares the structure for the next etching step, ensuring precise opening formation through stacked layers while maintaining process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents incomplete etching or overetching, ensuring uniformity and stability of the insulating layers, thereby reducing defects and improving the reliability of transistor connections and overall device performance.
Implementation Method 1
first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio
Data Source
AI summary
A method for etching an insulating layer includes: sequentially forming a first gate insulating layer, an amorphous silicon layer, a first interlayer insulating layer, and a second interlayer insulating layer on a substrate; applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process; first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas used in the first etching.