OLED Insulation Layer Structure Prevents Contact Hole Undercut

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Solution Overview

Problem

The formation of oxides on silicon semiconductor layers during heat treatment in OLED device manufacturing leads to under cut phenomena and profile failures in insulation layers, which can result in contact hole defects and increased contact resistance, especially when using buffered oxide etchant (BOE) processes.

Innovation Solution

An insulation layer structure comprising a first oxide-based layer with a slower etching rate, a nitride-based layer with a faster etching rate, and a third oxide-based layer with a similar etching rate to the first layer, is used to prevent under cut phenomena and ensure precise contact hole formation, while the third oxide layer directly contacts the active layer to enhance interface characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single-layer insulation layer is used during heat treatment, then the manufacturing process is simple, but under cut phenomena and profile failures occur in the contact hole

Engineering Contradiction:
Improveinsulation layer structureVSAvoidcontact hole profile
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The insulation layer is divided into three distinct layers: a first insulation layer (SiO2) at the bottom, a second insulation layer (Si3N4) in the middle, and a third insulation layer (SiO2) at the top. Each layer has different etching rates and provides specific functions, preventing under-cut phenomena while maintaining manufacturing feasibility through systematic segmentation of the insulation structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite insulation layer structure combining different materials (SiO2 and Si3N4) with complementary properties. The Si3N4 layer provides high etching resistance during BOE processing, while the SiO2 layers provide good interface characteristics with the active layer. This composite approach resolves the contradiction between ease of manufacture and manufacturing precision.

Inventive Principle:
Principle #40Composite materials

2Object-generated harmful factors

If buffered oxide etchant (BOE) process is used to remove oxides, then oxide removal is effective, but under cut phenomenon occurs in the insulation layer

Engineering Contradiction:
Improveoxide formationVSAvoidinsulation layer profile
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The second insulation layer (Si3N4) acts as an intermediary protective layer between the BOE etchant and the first insulation layer (SiO2). During the BOE process, the Si3N4 layer etches slower than SiO2, preventing the under-cut phenomenon that would otherwise occur in the SiO2 layer. This intermediary layer allows effective oxide removal while protecting the insulation layer profile.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies the second insulation layer (Si3N4) beforehand as a cushioning layer that resists etching during the BOE process. This pre-applied protective layer prevents the harmful under-cut effect from occurring in the underlying SiO2 layer, allowing the BOE process to effectively remove oxides without damaging the insulation layer structure.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If heat treatment is performed after contact hole formation, then semiconductor element performance is improved, but oxides form on the silicon semiconductor layer surface

Engineering Contradiction:
Improvesemiconductor element performanceVSAvoidoxide formation on silicon layer
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful oxide formation during heat treatment into a beneficial process by using the BOE etching step. The controlled formation of oxides during heat treatment is then utilized as a precursor for the subsequent BOE etching process, which selectively removes these oxides along with the sacrificial SiO2 layer, ultimately improving contact hole quality and semiconductor element performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution prevents under cut phenomena and profile failures, ensures reliable contact hole formation, and improves the interface characteristics of the active layer, leading to increased reliability and reduced manufacturing costs by allowing simultaneous heat treatment of both semiconductor elements.

Implementation Method 1

The insulation layer structure includes a first insulation layer having a first etching rate, a second insulation layer disposed on the first insulation layer and having a second etching rate that is greater than the first etching rate, and a third insulation layer disposed on the second insulation layer and having a third etching rate that is less than the second etching rate in a same etching process

Methodology Applied
Scientific EffectEtching rate difference:

Implementation Method 2

An under cut phenomenon may occur in an insulation layer located in the contact hole by the etchant of the BOE process

Methodology Applied
Scientific EffectChemical resistance:

Data Source

PatentUS10847594B2Organic light emitting display device
Publication Date: 2020.11.24 SAMSUNG DISPLAY CO LTD
  • US10847594B2 patent drawing
  • US10847594B2 patent drawing
  • US10847594B2 patent drawing

AI summary

An organic light emitting display device includes a substrate, a first semiconductor element, a second semiconductor element, an insulation layer structure, and a light emitting structure. The substrate has a first region and a second region that is adjacent to the first region. The insulation layer structure is disposed between a second gate electrode and a second active layer of the second semiconductor element. The insulation layer structure includes a first insulation layer having a first etching rate, a second insulation layer disposed on the first insulation layer and having a second etching rate that is greater than the first etching rate, and a third insulation layer disposed on the second insulation layer and having a third etching rate that is less than the second etching rate in a same etching process. The light emitting structure is disposed on the insulation layer structure.