OLED Node Line Parasitic Capacitance for Current Uniformity
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Solution Overview
Problem
OLED displays face issues with unintended deviations in current supply to multiple OLEDs due to variations in parasitic capacitance across the substrate, leading to luminance differences and display quality deterioration.
Innovation Solution
The OLED display design incorporates a substrate with distinct areas of varying parasitic capacitance by adjusting node line widths, overlapping areas, and dielectric constants, ensuring larger parasitic capacitance in central areas compared to exterior areas, which compensates for voltage drops and minimizes current deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform node line width and overlapping area are used across the substrate, then manufacturing process is simple, but parasitic capacitance varies due to voltage drops causing current deviation
Solution Approach 1:
The patent applies local quality by making the node line width and overlapping area position-dependent. Specifically, the node line in the central area of the substrate has a larger width and/or larger overlapping area with the electrode compared to the node line in the exterior area. This local variation compensates for the voltage drops that occur during signal transmission, ensuring that parasitic capacitance is sufficiently large in all regions to maintain current uniformity across the OLED display.
2Reliability
If node line overlaps electrode by large area, then parasitic capacitance increases suppressing current deviation, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the node line geometric parameters (width and/or length) and the overlapping area with the electrode based on position on the substrate. The node line in the central area has larger dimensions than in the exterior area. This controlled parameter variation ensures sufficient parasitic capacitance across the entire substrate while maintaining manufacturability through a systematic design approach.
3Reliability
If parasitic capacitance is increased to compensate voltage drops, then current deviation is suppressed, but device complexity increases
Solution Approach 1:
The patent applies local quality by making the node line width and overlapping area position-dependent. Specifically, the node line in the central area of the substrate has a larger width and/or larger overlapping area with the electrode compared to the node line in the exterior area. This local variation compensates for the voltage drops that occur during signal transmission, ensuring that parasitic capacitance is sufficiently large in all regions to maintain current uniformity across the OLED display.
Solution Approach 2:
The patent merges the function of the node line (signal transmission) with the function of generating parasitic capacitance (current compensation). By designing the node line to overlap with the electrode, the same conductive structure serves dual purposes: transmitting signals and generating the necessary parasitic capacitance to compensate for voltage drops and suppress current deviation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses current deviations across the substrate, minimizing luminance differences and maintaining display quality by compensating for voltage drops through increased parasitic capacitance in central areas.
Implementation Method 1
a node line connecting between any one and another of the plurality of thin film transistors and overlapping the electrode by a portion or more to form a parasitic capacitance together with the electrode
Data Source
AI summary
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate including a display area configured to display an image and a non-display area surrounding the display area. A plurality of OLEDs are positioned in the display area, each of the OLEDs including first and second electrodes spaced apart from each other. A plurality of pixel circuits are positioned in the display area, each of the pixel circuits including a plurality of thin film transistors (TFTs) and a node line electrically connected to at least two of the TFTs and at least partially overlapping the corresponding first electrode in the depth dimension of the OLED display so as to form a parasitic capacitor. The parasitic capacitor includes a first parasitic capacitor and a second parasitic capacitor, the first parasitic capacitor having a larger capacitance than that of the second parasitic capacitor.