OLED Display Panel Shielding Layout for Gate-Data Crosstalk
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the resolution of OLED display panels improves, the parasitic capacitance between the gate of the driving transistor and the data line increases, causing crosstalk due to voltage coupling, which needs to be addressed to maintain image quality.
Innovation Solution
A display panel design that includes a substrate, a driving transistor, a storage capacitor, and a shielding electrode with a fixed potential, where the orthographic projection of the gate is partially overlapped with the shielding electrode and partially with the capacitor plate, effectively shielding the lateral coupling capacitance between the data line and the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display panel is improved, then the display quality is enhanced, but the parasitic capacitance between the gate of the driving transistor and the data line increases, causing crosstalk
Solution Approach 1:
The patent introduces a shielding electrode as an intermediary element positioned between the data line and the gate of the driving transistor. This shielding electrode acts as a mediator to block the electric field coupling between the data line and gate, thereby reducing parasitic capacitance and crosstalk while maintaining high display resolution
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple metal layers at different heights. The shielding electrode is positioned in a specific metal layer above or below the data line and gate, creating spatial separation in the vertical dimension to reduce lateral parasitic capacitance while preserving horizontal resolution
2Measurement precision
If the layout space for pixels is reduced to improve resolution, then more pixels can be displayed, but the parasitic capacitance between the gate and data line becomes larger
Solution Approach 1:
By introducing a vertical stacking structure with multiple metal layers, the patent separates the data line and gate in the vertical dimension while keeping them close in the horizontal dimension. This allows pixel electrodes to be arranged more densely horizontally (improving resolution) while the vertical separation minimizes parasitic capacitance
3Ease of operation
If voltage changes in the data line are coupled to the gate of the driving transistor, then signal transmission occurs, but crosstalk is caused
Solution Approach 1:
The shielding electrode serves as an intermediary that blocks unwanted voltage coupling from the data line to the gate. It allows necessary signal transmission to the pixel electrode while preventing parasitic voltage changes from coupling into the driving transistor gate, thereby maintaining voltage stability and reducing crosstalk
Solution Approach 2:
The patent extracts and separates the harmful parasitic capacitance component by introducing the shielding electrode. The shielding electrode selectively blocks the coupling path for unwanted voltage changes while maintaining the necessary signal transmission path, effectively removing the harmful crosstalk component
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design mitigates the influence of voltage changes in the data line on the gate of the driving transistor, maintaining a stable voltage waveform and reducing crosstalk, as demonstrated by a 48% reduction in parasitic capacitance and significant crosstalk mitigation.
Implementation Method 1
a first shielding electrode having a fixed potential, wherein a part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate
Implementation Method 2
a lateral parasitic capacitance between the gate and the data line is unavoidable
Data Source
AI summary
A display panel includes a substrate; a first metal layer comprising a gate of a driving transistor; a second metal layer comprising a capacitor plate of a storage capacitor; a third metal layer, located on one side of the second metal layer away from the substrate and comprising a data line. An orthographic projection of the data line on the substrate is non-overlapped with the orthographic projection of the gate projected on the substrate; and a first shielding electrode, having a fixed potential. A part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate, and the rest part of the orthographic projection of the gate projected on the substrate is located in the orthographic projection of the capacitor plate projected on the substrate.