OLED Display Panel Shielding for Data Lead Overlap
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Solution Overview
Problem
The overlap between data leads and pixel driving sub-circuits in OLED display panels generates parasitic capacitance, affecting the potential of driving transistors and causing brightness uniformity issues in the display panel.
Innovation Solution
Incorporating a shielding layer with a constant voltage signal, such as the first shielding pattern, between the data leads and driving transistors to isolate them and stabilize the transistor potential, thereby improving brightness uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If data leads are routed through the middle area overlapping with driving transistor electrodes, then the frame width can be reduced, but parasitic capacitance increases and driving transistor potential becomes unstable
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the data lead and the driving transistor. This shielding layer is connected to a reference potential and creates a protective barrier that blocks parasitic capacitance coupling, thereby stabilizing the driving transistor potential while allowing the data lead to pass through the overlapping region
Solution Approach 2:
The shielding layer is positioned in advance to prevent the harmful effect of parasitic capacitance before it can affect the driving transistor. By establishing this protective structure beforehand, the potential instability caused by data lead overlap is preemptively counteracted
2Device complexity
If data leads overlap with pixel driving sub-circuits, then routing complexity is reduced, but brightness uniformity deteriorates due to parasitic capacitance
Solution Approach 1:
The shielding layer acts as a mediator that allows the data lead to maintain its simplified routing path through the pixel area while simultaneously protecting the pixel driving sub-circuit from parasitic capacitance effects, thereby preserving brightness uniformity without increasing routing complexity
Solution Approach 2:
The shielding structure is applied locally at specific regions where data leads overlap with pixel driving sub-circuits, providing targeted protection against parasitic capacitance only where needed, rather than requiring comprehensive shielding throughout the entire display panel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding layer enhances the stability of driving transistors and improves brightness uniformity in the display panel while maintaining a narrow frame design.
Implementation Method 1
The overlap between data leads and pixel driving sub-circuits in OLED display panels generates parasitic capacitance, affecting the potential of driving transistors
Data Source
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AI summary
Disclosed is a display panel. The display panel comprises a display area, and the display area comprises a middle area and two edge areas. The display panel comprises a base substrate and a driving circuit layer. The driving circuit layer comprises a plurality of pixel circuit units, a plurality of data write signal lines, a plurality of data leads, and a shielding layer. The plurality of data write signal lines are located in the display area; each data lead comprises a first lead segment and a second lead segment; one end of the first lead segment is electrically connected to one data write signal line located in the edge area, and the other end of the first lead segment is electrically connected to one end of the second lead segment; and the second lead segment is located in the middle area. The orthographic projection of the second lead segment on the base substrate at least partially overlaps with the orthographic projection of a first electrode of at least one driving transistor on the base substrate. The shielding layer is configured to have a constant voltage signal. The shielding layer comprises at least one first shielding pattern, and the first shielding pattern is located between the first electrode of the driving transistor and the second lead segment.