OLED Pixel Wiring Layout for Reduced Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Unintentional capacitances between wires in light emitting diode displays lead to image quality deterioration and luminance deviations due to process dispersion, which existing technologies have not effectively addressed.
Innovation Solution
A display device design that includes a substrate with a semiconductor layer, a gate conductive layer, and a data conductive layer featuring specific connecting members and shielding patterns to reduce capacitance between the light emitting control line and the gate electrode of the driving transistor, thereby minimizing luminance deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire layout is used in LED display, then device structure is simple, but capacitance between light emitting control line and gate electrode increases causing image quality deterioration and luminance deviation
Solution Approach 1:
The first data conductive layer is divided into multiple connecting members (first connecting member, second connecting member, third connecting member) that are spatially separated and positioned at different locations relative to the gate electrode and control line. This segmentation allows each connecting member to serve specific functional purposes while reducing overall capacitance between the control line and gate electrode, thereby improving image quality without excessive structural complexity
Solution Approach 2:
The first connecting member acts as an intermediary element positioned between the light emitting control line and the gate electrode. By introducing this intermediate conductive structure with specific geometry (recessed opening and hole opening), the patent reduces direct capacitive coupling while maintaining necessary electrical connections, thus reducing luminance deviation caused by process dispersion
2Reliability
If wire spacing is increased to reduce capacitance, then capacitance between control line and gate electrode decreases, but device area increases
Solution Approach 1:
The connecting members utilize vertical layering and three-dimensional positioning rather than simply increasing horizontal spacing. The first connecting member extends in the second direction (perpendicular to the first direction) and is positioned at specific heights relative to the gate electrode and control line. This dimensional approach reduces capacitance through spatial arrangement in multiple dimensions while maintaining compact pixel area
Solution Approach 2:
The connecting members have non-uniform geometries with recessed openings and hole openings positioned at specific locations. The first connecting member has a recessed opening adjacent to the gate electrode and a hole opening positioned between the gate electrode and control line. This local variation in conductive structure properties reduces capacitance in critical areas while maintaining connectivity where needed, achieving luminance uniformity without excessive area expansion
Data Source
AI summary
A display device includes: a substrate; a semiconductor layer disposed on the substrate; a gate conductive layer disposed on the semiconductor layer; and a first data conductive layer disposed on the gate conductive layer, wherein the gate conductive layer includes a first scan line and a light emitting control line extending along a first direction, and a first gate electrode disposed between the first scan line and the light emitting control line in a plan view, the first data conductive layer includes a first connecting member overlapping the first gate electrode, the first connecting member includes a recessed opening and a hole opening, and a part of the hole opening is disposed between the first gate electrode and the light emitting control line in a plan view.