OLED Pixel Driving Circuit Layout for Stable Current and Low Leakage
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Solution Overview
Problem
Existing OLED display technologies face challenges in maintaining consistent driving current for pixel units, leading to inefficiencies and potential leakage through driving transistors.
Innovation Solution
The array substrate incorporates a specific configuration of pixel driving circuits with transistors and capacitors, including a third node connecting line that overlaps with control signal lines, and additional reset transistors to manage and stabilize the driving current, preventing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pixel driving circuit is used in OLED display, then the circuit structure is simple, but the driving current is not stable and leakage occurs through the driving transistor
Solution Approach 1:
The pixel driving circuit is segmented into multiple functional blocks: a driving transistor for current control, a compensation transistor for threshold voltage compensation, a reset transistor for node resetting, and storage capacitors for voltage holding. Each segment performs a specific function to collectively achieve stable driving current while managing circuit complexity through modular design.
Solution Approach 2:
The compensation transistor performs preliminary action by compensating for the driving transistor's threshold voltage before the driving current is established. The reset transistor also performs preliminary resetting of the storage node to ensure proper initial conditions. These preliminary actions prevent subsequent instability and leakage issues during normal operation.
2Ease of manufacture
If the third node connecting line overlaps with control signal lines in the same layer, then the manufacturing process is simplified, but signal interference may occur
Solution Approach 1:
The third node connecting line is positioned in the same layer as control signal lines (G3 layer), but the patent resolves potential interference by careful spatial routing and positioning. The connecting line is directed toward the second electrode of the data write transistor while control signal lines are routed to gate electrodes, ensuring functional separation despite layer co-location. This dimensional approach simplifies manufacturing by avoiding additional layer complexity.
3Reliability
If additional reset transistors and capacitors are added to stabilize driving current, then current stability improves, but the pixel circuit area increases
Solution Approach 1:
The first capacitor electrode, fourth capacitor electrode, and third node are merged into a common conductive structure that serves multiple functions: storing voltage for the first capacitor, storing voltage for the second capacitor, and providing a reset node. This merging reduces the total area required compared to completely separate structures while maintaining the stability benefits of additional capacitive elements.
Solution Approach 2:
The third reset transistor serves multiple functions: resetting the third node (common to both capacitors), preparing the data write transistor for the next frame, and maintaining proper voltage levels at the anode of the light emitting element. This multi-functionality justifies the area occupation by providing comprehensive control with a single transistor rather than requiring separate transistors for each function.
Data Source
AI summary
An array substrate includes a plurality of pixel driving circuits and a plurality of third control signal lines. A respective pixel driving circuit includes a data write transistor, a compensating transistor, a third reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a third node connecting line. A respective third control signal line is configured to provide control signals to a gate electrode of the third reset transistor. The third node connecting line is connected to second electrodes of the compensating transistor and the data write transistor, and to the first capacitor electrode and the fourth capacitor electrode. An orthographic projection of the third node connecting line on a base substrate at least partially overlaps with an orthographic projection of the respective third control signal line on the base substrate.