OLED Pixel Circuit Scan Circuit Reduction

The patent merges the control of both LTPS P-type and IGZO N-type transistors under a unified scan circuit architecture. By using two N-type transistors (first and second N-type transistors) that can be controlled by the same scan signal, the design consolidates what would otherwise require separate scan circuits, thereby reducing the total number of scan circuits from three to two while maintaining the low leakage current benefit of combining both transistor types.

The scan signal terminal is designed to serve multiple functions by controlling both the first N-type transistor and the second N-type transistor through the same scan signal. This multi-functional approach allows a single scan circuit to manage multiple transistor operations (initialization and data writing) that would traditionally require separate dedicated circuits, thus reducing overall circuit complexity while preserving the low leakage characteristics.

The patent combines the control functions for both transistor types into a unified scan circuit system. The first N-type transistor and second N-type transistor are both controlled by scan signals from the same scan circuit, merging what would otherwise be separate control paths. This consolidation reduces the peripheral driver circuit complexity from three sets of scan circuits to two sets, while maintaining reliable control over both LTPS and IGZO transistors through coordinated switching.

The first N-type transistor performs preliminary initialization of the first node before the data writing operation. By pre-initializing the node to a known state (first initialization stage), the circuit ensures reliable subsequent data writing and drive operations without requiring additional reset circuits. This preliminary action streamlines the overall control sequence and reduces the need for multiple independent control circuits.