OLED Display Pixel Clocking for Lower Power and Rapid Response

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Solution Overview

Problem

Existing display devices face challenges in reducing power consumption while maintaining rapid response speed, particularly in organic light emitting display devices.

Innovation Solution

The display device incorporates a plurality of pixel groups connected to a shared scan line and receives different clock signals, with activation periods of these clock signals being in a non-overlap state to optimize power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a shared scan line is used to connect multiple pixel groups, then device complexity is reduced, but power consumption control becomes less efficient

Engineering Contradiction:
Improvenumber of scan linesVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The pixel group connected to the shared scan line is divided into multiple sub-pixel groups (first, second, third, fourth sub-pixel groups), each receiving data from separate data lines. This segmentation allows independent control of data input while sharing the scan line, resolving the contradiction between reducing scan line count and maintaining power control efficiency.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If multiple data lines are used to connect to pixel groups, then power consumption is reduced through selective activation, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidnumber of data lines
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Multiple data lines (first, second, third, fourth data lines) are merged into a single shared scan line for scanning control. This combining approach reduces the complexity of scan line routing while maintaining the power-saving benefits of selective data line activation, as the scan line can sequentially activate different sub-pixel groups connected to different data lines.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If pixel groups are activated simultaneously, then response speed is improved, but power consumption increases

Engineering Contradiction:
Improveresponse speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The pixel groups are activated in periodic sequences rather than simultaneously. The shared scan line sequentially scans through different sub-pixel groups, and data lines are activated in corresponding sequences. This periodic activation maintains rapid response through efficient sequential updating while significantly reducing power consumption by keeping most pixels inactive at any given moment.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces power consumption without compromising response speed by efficiently managing pixel activation through staggered clock signal timings.

Implementation Method 1

The light emitting element may generate light through the recombination of an electron and a hole

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Data Source

PatentUS20250252917A1Display device
Publication Date: 2025.08.07 SAMSUNG DISPLAY CO LTD
  • US20250252917A1 patent drawing
  • US20250252917A1 patent drawing
  • US20250252917A1 patent drawing

AI summary

A display device includes a plurality of data lines and a plurality of pixels. Each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor to receive a first scan signal, third transistors. The plurality of data lines include a plurality of first group data lines and a plurality of second group data lines. The plurality of pixels include a plurality of first group pixels connected to the plurality of first group data lines and a plurality of second group pixels connected to the plurality of second group data lines. The first scan signal and a first clock signal are applied to different transistors of the third transistors.