OLED Pixel Compensation Circuit Horizontal Size Reduction
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Solution Overview
Problem
The existing pixel compensation circuits in OLED display devices, such as 7T1C, 6T1C, and 6T2C structures, limit the increase in pixels per inch (PPI) due to the size constraints imposed by the layout of components, particularly the polysilicon traces for active layers of transistors, which result in reduced pixel density and uneven brightness.
Innovation Solution
A pixel compensation circuit design where the fourth and seventh transistors are controlled by the same scanning signal line, connected to the reset voltage signal line, and share active layers, with polysilicon traces arranged in a vertical direction, reducing the horizontal size of the pixel structure and allowing for higher PPI density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional pixel compensation circuits (7T1C, 6T1C, 6T2C) are used with separate scanning signal lines for fourth and seventh transistors, then each transistor can be independently controlled, but the polysilicon traces form S-shaped patterns that increase the horizontal size of the pixel structure
Solution Approach 1:
The patent merges the control of the fourth and seventh transistors by connecting both to the same scanning signal line (Scan(n)), eliminating the need for separate scanning signal lines and reducing the horizontal space required for polysilicon traces in the pixel structure
Solution Approach 2:
The patent reconfigures the polysilicon trace layout to extend primarily in the vertical direction rather than forming S-shaped horizontal patterns, changing the dimensional orientation of the active layer traces to reduce horizontal pixel size
2Manufacturing precision
If polysilicon traces are arranged in S-shaped patterns for fourth and seventh transistors, then each transistor has its own dedicated trace path, but the pixel density and PPI are reduced due to increased horizontal size
Solution Approach 1:
The patent combines the polysilicon trace paths for the fourth and seventh transistors, allowing them to share vertical trace routing rather than requiring separate S-shaped horizontal paths, thereby increasing pixel density and PPI
Solution Approach 2:
The patent transitions from horizontal S-shaped trace patterns to vertical trace arrangements, utilizing the vertical dimension more effectively to accommodate multiple transistor connections without increasing horizontal pixel size
3Productivity
If the pixel structure size is reduced to increase PPI, then higher pixel density is achieved, but the layout of components becomes more constrained and complex
Solution Approach 1:
The patent simplifies the pixel layout by reorienting polysilicon traces to extend vertically rather than horizontally, providing more flexible space arrangement within the pixel structure and reducing layout complexity despite reduced pixel size
Data Source
AI summary
A pixel compensation circuit and an OLED display device are disclosed. Two or more TFTs are controlled by the scanning signal output from the scanning signal line in the same row in the pixel compensation circuit proposed by the present disclosure. Further, the OLED and the storage capacitor are both connected to the reset voltage signal line. So the OLED and the storage capacitor are reset after receiving the reset voltage signal. The size of the pixel structure in the horizontal direction is compressed in the pixel compensation circuit of the present disclosure, thereby providing space for the improvement of the PPI and facilitating the design of the high PPI panel successfully.