OLED Pixel Layout Shielding Data-Line Crosstalk

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Solution Overview

Problem

High-resolution OLED displays face limitations in minimizing vertical crosstalk due to parasitic capacitance between the driving gate node and data line, which affects the driving current and luminance, especially in smaller pixel sizes.

Innovation Solution

The OLED display incorporates a configuration where the driving connecting member is spaced apart from the data line with either the initialization voltage line or the driving voltage line interposed between them, reducing parasitic capacitance and minimizing changes in the driving gate voltage, thereby reducing vertical crosstalk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the distance between the data line and the driving gate node is increased to minimize vertical crosstalk, then the parasitic capacitance is reduced, but the pixel size increases which is not suitable for high-resolution displays

Engineering Contradiction:
Improvevertical crosstalkVSAvoidpixel size
Core Design Contradiction:
Object-affected harmful factorsVSArea of moving object

Solution Approach 1:

The patent introduces an initialization voltage line as an intermediary element positioned between the data line and the driving gate node. This intermediate conductive structure acts as a shield that reduces the parasitic capacitance coupling between the data line and driving gate node, thereby minimizing vertical crosstalk without requiring increased spacing that would enlarge the pixel area.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the pixel size is reduced to achieve high resolution, then the display resolution is improved, but the vertical crosstalk increases due to limited spacing between data line and driving gate node

Engineering Contradiction:
Improvedisplay resolutionVSAvoidvertical crosstalk
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

By placing the initialization voltage line between the data line and driving gate node, the patent provides an intermediate shielding structure that reduces parasitic capacitance effects. This allows the driving gate node to be positioned closer to the data line, enabling smaller pixel sizes and higher display resolution while maintaining low vertical crosstalk levels.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of moving object

If the driving gate node is positioned closer to the data line to reduce pixel area, then the pixel size is reduced for high resolution, but the parasitic capacitance increases causing voltage changes

Engineering Contradiction:
Improvepixel areaVSAvoiddriving gate voltage stability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The initialization voltage line serves as an intermediate shield between the data line and driving gate node, reducing the parasitic capacitance coupling. This shielding effect stabilizes the driving gate voltage by minimizing voltage changes caused by data line switching, even when the driving gate node is positioned close to the data line to reduce pixel area.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The initialization voltage line is configured to maintain a stable potential between the data line and driving gate node, creating an equipotential shielding effect that reduces voltage fluctuations on the driving gate node caused by data line switching, thereby improving voltage stability.

Inventive Principle:
Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the driving range of the gate-source voltage, allowing for finer control of light gray levels and improved resolution and display quality by minimizing kickback voltage and vertical crosstalk.

Implementation Method 1

due to a parasitic capacitance formed between a driving gate node connected to a driving gate electrode of the driving transistor and a data line, a voltage change of the data line influences a voltage of the driving gate node

Methodology Applied
Scientific EffectParasitic capacitance: Capacitance

Data Source

PatentUSRE49899E1Display device
Publication Date: 2024.04.02 SAMSUNG DISPLAY CO LTD
  • USRE49899E1 patent drawing
  • USRE49899E1 patent drawing
  • USRE49899E1 patent drawing

AI summary

An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a plurality of pixels and a data line formed adjacent to the pixels and configured to transfer a data voltage. The display also includes a driving voltage line formed substantially parallel to the data line and configured to transfer a driving voltage, and an initialization voltage line formed substantially parallel to the data line and configured transfer an initialization voltage. At least one of the pixels includes a driving transistor including a driving gate electrode and configured to receive the initialization voltage from the initialization voltage line. A driving connector is spaced apart from the data line and electrically connected to the driving gate electrode. An OLED is electrically connected to the driving transistor, at least one of the initialization voltage line and the driving voltage line interposed between the driving connector and the data line.