OLED Pixel Circuit Drain Node Potential Control
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Solution Overview
Problem
Existing electro-optical devices face challenges in achieving low power consumption while maintaining display quality due to charges remaining in the drain node of transistors, which lead to parasitic capacitance issues and increased power consumption when resetting potentials.
Innovation Solution
The electro-optical device employs a pixel circuit with a first transistor that sets the data line to a specific potential during initialization, adjusts the gate node to threshold voltage during compensation, and sets the drain node to a potential greater than or equal to the data line potential but less than the gate node potential during the drain set period, preventing charge flow into the light-emitting element during light-emission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset potential is supplied to the drain node of the transistor via the data line, then the charge remaining in the parasitic capacitance is cleared, but the potential amplitude of the data line increases leading to increased power consumption
Solution Approach 1:
The patent divides the data line potential control into multiple stages: initialization period (setting data line to first potential), compensation period (setting gate node to second potential), first period (setting gate node to third potential), and second period (setting drain node to fourth potential). This segmentation allows independent optimization of each control stage to resolve the contradiction between clearing parasitic capacitance charges and minimizing data line potential amplitude.
Solution Approach 2:
The patent applies preliminary actions by setting the data line to a first potential during the initialization period before light emission, and setting the drain node to a fourth potential during the second period before light emission. These preliminary potential settings clear charges in the parasitic capacitance in advance, preventing residual charge effects during light emission while allowing the data line potential to return to a lower state afterward, thus reducing overall power consumption.
2Use of energy by moving object
If the data line potential amplitude is reduced to achieve low power consumption, then power consumption decreases, but the ability to clear charges from the drain node is compromised
Solution Approach 1:
The patent introduces the gate node as an intermediary element to transfer the charge clearing function from the data line to the gate node. By setting the gate node to a second potential corresponding to the threshold voltage during the compensation period, and then to a third potential corresponding to the desired luminance during the first period, the patent clears charges from the drain node through the gate node's control action rather than directly through large data line potential swings, thus reducing power consumption while maintaining display quality.
3Illumination intensity
If the gate node is set to a high potential to ensure proper light emission, then light emission is guaranteed, but residual charges in the drain node cause slight light emission and deteriorate contrast ratio
Solution Approach 1:
The patent applies preliminary anti-action by setting the drain node to a fourth potential greater than or equal to the first potential and smaller than the third potential during the second period before light emission. This preliminary potential setting counteracts the accumulation of residual charges in the parasitic capacitance at the drain node, preventing them from flowing to the light-emitting element during light emission. This ensures that when the gate node is set to the third potential for proper light emission, the contrast ratio is maintained by preventing unwanted residual charge effects.
Data Source
AI summary
A pixel circuit provided in correspondence with a scanning line and a data line includes a transistor and an OLED, where the transistor supplies current corresponding to a voltage between a gate node and a source node to the OLED in a light-emission period, sets the data line to a potential Vini in an initialization period, sets the gate node of the transistor to a threshold equivalent potential in a compensation period, sets the gate node of the transistor to a potential corresponding to a luminance of the OLED from the threshold equivalent potential in a write period, and sets the drain node of the transistor to a potential greater than or equal to the potential Vini and lower than a potential VBk in a drain set period.