OLED Pixel Driving Circuit with Segmented Adjusting Stages
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Solution Overview
Problem
Current OLED display technologies cannot fine-tune the device characteristics of driving transistors at different stages, affecting the optical performance and leading to issues like hysteresis and smear in image display.
Innovation Solution
Incorporating a data writing circuit and an adjusting circuit in the pixel driving circuit, with specific stages for adjusting signals during the data writing period, allowing for fine regulation of the driving transistor's state to eliminate the influence of previous frames and improve image clarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional pixel driving circuit is used without adjusting circuits, then the device structure is simple, but the driving transistor characteristics cannot be fine-tuned at different stages, leading to hysteresis and smear in image display
Solution Approach 1:
The data writing period is segmented into three distinct stages: first adjusting stage, data writing stage, and second adjusting stage. Each stage performs a specific function - the first adjusting stage initializes transistor characteristics, the data writing stage writes image data, and the second adjusting stage fine-tunes the characteristics. This segmentation allows precise control of driving transistor characteristics at different temporal points, resolving the contradiction between control precision and structural simplicity.
Solution Approach 2:
The first adjusting stage is performed before the data writing stage to pre-establish the driving transistor's operating characteristics. By conducting this preliminary adjustment, the transistor is prepared in an optimal state before receiving image data, ensuring consistent and accurate display performance while maintaining a relatively simple circuit structure.
2Reliability
If multiple adjusting stages are introduced in the data writing period, then image clarity and hysteresis reduction are improved, but the control complexity and time consumption increase
Solution Approach 1:
The data writing period is organized as a periodic sequence of three stages that repeat for each frame refresh. This periodic structure ensures that the driving transistor characteristics are consistently adjusted at the same points in each cycle, maintaining reliable image quality while keeping the total time consumption predictable and manageable through efficient stage transitions.
Solution Approach 2:
The adjusting operations are performed in rapid succession during dedicated adjusting stages, and the circuit quickly transitions to the data writing stage. This approach rushes through the necessary adjustments efficiently without unnecessary delays, ensuring high image quality while minimizing the time lost to adjustment operations.
3Productivity
If the driving transistor state is not refreshed between frames, then the circuit operation is continuous and simple, but hysteresis effects accumulate and degrade image quality
Solution Approach 1:
The patent converts the natural drift and hysteresis effects of the driving transistor into a controllable parameter by introducing adjusting stages. Instead of viewing transistor state changes as harmful, the system uses these changes as an opportunity to deliberately reset and standardize the transistor characteristics, turning a potential source of image degradation into a mechanism for maintaining consistent display quality across frames.
Data Source
AI summary
A display panel, a method for driving the same, and a display apparatus are provided. A pixel driving circuit includes a driving transistor, a data writing circuit, and an adjusting circuit. The driving transistor has a gate electrically connected to a first node, and first and second electrodes respectively electrically connected to a second node and a third node. An operating period of the pixel driving circuit comprises a data writing period including first and second adjusting stages and a data writing period between the first and second adjusting stages. A data writing circuit is configured to provide a data signal to the second node during the data writing period. An adjusting circuit is configured to provide a first adjusting signal to the second node or the third node during the first adjusting stage, and to provide a second adjusting signal to the second node during the second adjusting stage.