OLED Pixel Isolation Structure for ESD Damage Containment
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Solution Overview
Problem
Display devices face challenges in maintaining reliability and minimizing damage from external impacts and electrostatic discharge, which can cause damage to pixels and propagate to other areas.
Innovation Solution
The display device incorporates a specific layered structure with a substrate, semiconductor layers, gate insulating layers, storage electrodes, and interlayer insulating layers, including organic materials to create isolated pixel circuit regions and prevent damage propagation, using a cross-section width that decreases toward the substrate and filling openings with organic insulating layers to separate semiconductor layers and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous semiconductor layer structure is used across pixel regions, then manufacturing is simpler, but damage from external impacts and electrostatic discharge can propagate to adjacent pixels
Solution Approach 1:
The patent divides the continuous semiconductor layer into separate isolated regions using openings that extend through multiple insulating layers. These openings create physical separations between adjacent pixel circuit regions, preventing damage propagation while maintaining manufacturing feasibility through a systematic layered approach.
Solution Approach 2:
The patent implements nested openings where an opening in the first interlayer insulating layer is positioned to surround an opening in the second gate insulating layer, which in turn surrounds an opening in the first gate insulating layer. This nested structure creates multiple levels of isolation, enhancing pixel protection while managing structural complexity through hierarchical design.
2Reliability
If openings extend through multiple insulating layers to isolate semiconductor layers, then pixel circuit regions are effectively separated, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms openings in the first gate insulating layer and second gate insulating layer before forming the interlayer insulating layers. This preliminary action establishes the isolation structure early in the manufacturing process, allowing subsequent layers to be formed around predefined openings, thereby reducing alignment complexity and precision requirements during later manufacturing steps.
Solution Approach 2:
The patent applies different opening configurations at different locations: openings in lower layers are positioned to surround openings in upper layers, creating localized isolation zones. This local quality approach allows precise isolation where needed while maintaining simpler structures in other areas, balancing manufacturing precision requirements with effective pixel separation.
3Reliability
If the cross-section width of openings decreases toward the substrate, then semiconductor layers are better isolated, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric opening geometries where the cross-section width decreases toward the substrate, creating a tapered profile. This asymmetric design provides effective isolation by narrowing the opening at the critical interface with the semiconductor layer while maintaining a wider opening at the top for easier manufacturing access and alignment, thus balancing isolation effectiveness with manufacturing simplicity.
Data Source
AI summary
An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening. The data line and the driving voltage line are positioned on the second interlayer insulating layer. The semiconductor layer, the gate electrode, and the storage electrode are included in a pixel region. The display device includes a plurality of pixel regions. The data line and the driving voltage line cross the pixel circuit region. A portion of the semiconductor layer is in contact with the second interlayer insulating that fills the opening.