OLED Pixel Circuit Hysteresis Compensation via Detour Transistor
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Solution Overview
Problem
Active matrix organic light emitting display devices face reduced response time due to hysteresis in driving transistors, leading to decreased definition and motion blur, as the transistor curve shifts during continuous off-voltage periods, preventing target luminance from being reached effectively.
Innovation Solution
Incorporating a sixth transistor connected in parallel to the organic light emitting diode, which forms a current path during initialization to supply initialization voltage to the gate electrode of the driving transistor, thereby compensating for hysteresis and preventing increased black luminance, thus improving response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional pixel circuit with driving transistor is used, then the device structure is simple, but the response time is slow due to hysteresis causing definition loss and motion blur
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks: a driving transistor for luminance control, a sixth transistor connected in parallel to the OLED for hysteresis compensation, and a detour current path. This segmentation allows independent optimization of driving function and compensation function, improving response time without overwhelming complexity
Solution Approach 2:
The sixth transistor acts as an intermediary element connected in parallel to the OLED. It provides a detour current path that compensates for hysteresis effects in the driving transistor by supplying additional current during the initialization period, thereby improving response time without directly modifying the driving transistor itself
2Speed
If initialization voltage is supplied to compensate hysteresis, then response time is improved, but black luminance may increase
Solution Approach 1:
The compensation mechanism operates periodically during the initialization period before each frame display. The sixth transistor is activated only during this specific time window to supply initialization voltage and compensate hysteresis, then deactivated during normal display to prevent black luminance increase. This periodic operation achieves response time improvement without compromising display quality
Solution Approach 2:
The detour current path through the sixth transistor provides preliminary compensation for hysteresis effects before the actual display occurs. By pre-charging the gate electrode of the driving transistor during the initialization period, the system prepares the driving transistor to respond faster to luminance changes without causing unwanted black luminance during normal operation
Data Source
Figure 1
Figure 2~3
Figure 4A~4B
AI summary
A pixel having an improved response time includes an organic light emitting diode connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the organic light emitting diode, the first transistor including a gate electrode connected to a first node; a second transistor connected between a first electrode of the first transistor connected to the first power supply and a data line, the second transistor including a gate electrode connected to a current scanning line; a third transistor connected between a second electrode of the first transistor connected to the organic light emitting diode and the first node, the third transistor including a gate electrode connected to the current scanning line; a fourth transistor connected between the second electrode of the first transistor and the organic light emitting diode, the fourth transistor including a gate electrode connected to a light emitting control line; a fifth transistor connected between the second power supply or a third power supply that is an initialization power supply and the first node, the fifth transistor including a gate electrode connected to a previous scanning line; a sixth transistor connected between the second power supply or the third power supply and the fourth transistor, the sixth transistor including the gate electrode connected to the previous scanning line; and a storage capacitor connected between the first power supply and the first node.