OLED Pixel Circuit Layout for Kickback Voltage Compensation

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Solution Overview

Problem

In organic light-emitting display devices, the voltage of the gate electrode of a transistor can be excessively reduced due to kickback voltage characteristics, which complicates the implementation of black luminance and may require reducing supply voltages beyond conventional power supply limits.

Innovation Solution

The design includes a display device with a light-emitting diode, transistors, and parasitic capacitors, where the conductive pattern overlaps scan lines, increasing the overlapping area and capacitance, and using PMOS and NMOS transistors in combination to manage kickback voltages, preventing excessive reduction of the gate electrode voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PMOS transistors are replaced with NMOS transistors or used in combination, then device performance and black luminance implementation are improved, but gate electrode voltage becomes excessively reduced due to kickback voltage characteristics

Engineering Contradiction:

Improveblack luminance implementationVSAvoidkickback voltage

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a conductive pattern that overlaps with scan lines to generate parasitic capacitance. This parasitic capacitance is deliberately used to counteract the harmful kickback voltage effect, converting the previously problematic voltage reduction into a beneficial compensation mechanism that stabilizes the gate electrode voltage.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The conductive pattern acts as an intermediary element between the scan lines and the gate electrode. It introduces parasitic capacitance that serves as a buffer, mediating the voltage fluctuations caused by kickback and preventing excessive voltage reduction at the gate electrode.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If supply voltage is reduced to implement black luminance, then display performance is improved, but power supply limits are exceeded and manufacturing complexity increases

Engineering Contradiction:

Improveblack luminance implementationVSAvoidpower supply requirements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The conductive pattern with parasitic capacitance provides self-compensation for kickback voltage effects. The system uses its own inherent parasitic elements rather than requiring external voltage adjustment or complex power supply circuits, thereby maintaining compatibility with conventional power supply limits while achieving black luminance.

Inventive Principle:

Principle #25Self-service

3Reliability

If conductive pattern overlaps scan lines, then parasitic capacitance increases and kickback compensation is improved, but device area increases

Engineering Contradiction:

Improvegate voltage stabilityVSAvoidconductive pattern area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The conductive pattern is merged with existing scan line structures, utilizing the same physical space and manufacturing layers. By overlapping rather than adding separate structures, the patent achieves parasitic capacitance compensation without proportionally increasing the overall device area.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively prevents the excessive reduction of the gate electrode voltage, enabling the implementation of black luminance using conventional external voltage sources, thereby reducing manufacturing costs and improving display performance.

Implementation Method 1

the conductive pattern overlaps the first scan line and the second scan line... a first parasitic capacitor formed between the gate electrode of the second transistor and the gate electrode of the first transistor; and a second parasitic capacitor formed between the gate electrode of the third transistor and the gate electrode of the first transistor

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS11783783B2Display device

Publication Date: 2023.10.10 SAMSUNG DISPLAY CO LTD

AI summary

A display device including a light-emitting diode, a first transistor, a second transistor, a data line connected to the second transistor and configured to transmit a data signal, a third transistor, a first signal line connected to a gate electrode of the second transistor and configured to transmit a first signal, a second signal line connected to a gate electrode of the third transistor and configured to transmit a second signal, and a connect portion connected to a gate electrode of the first transistor and an electrode of the third transistor, in which the connect portion overlaps the first signal line and the second signal line, and an overlapping area between the connect portion and the first signal line is different from an overlapping area between the connect portion and the second signal line.