OLED Pixel Circuit Layer Layout to Reduce Parasitic Capacitance
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Solution Overview
Problem
In high-resolution OLED display panels, the reduction in pixel circuit size leads to increased parasitic capacitance between signal lines, causing interference and unsatisfactory display effects due to the close proximity of the first connection structure and data line in the same layer.
Innovation Solution
The array substrate design features the first connection structure and data line in different layers, with a compact layout where they extend along a first direction and have opposite orthographic projections on the base substrate, reducing parasitic capacitance and signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the first connection structure and data line are placed in the same layer to simplify manufacturing, then device complexity is reduced, but parasitic capacitance increases causing signal interference
Solution Approach 1:
The patent applies dimensionality change by moving the first connection structure and data line from the same layer to different layers in the vertical dimension. Specifically, the data line is positioned in the fourth conductive layer while the first connection structure is positioned in the third conductive layer, separated by a fourth insulating layer. This vertical separation reduces parasitic capacitance between these conductive elements while maintaining a compact pixel circuit layout.
2Manufacturing precision
If pixel circuit size is reduced to achieve high resolution, then display quality improves, but parasitic capacitance between signal lines increases causing interference
Solution Approach 1:
The patent uses vertical layering to separate signal lines that would otherwise be forced into close proximity in the horizontal plane. By positioning the data line in the fourth conductive layer and the first connection structure in the third conductive layer, the design achieves high pixel density while maintaining adequate vertical separation to minimize parasitic capacitance and signal interference.
Solution Approach 2:
The fourth insulating layer acts as an intermediary between the third conductive layer (containing the first connection structure) and the fourth conductive layer (containing the data line). This insulating layer provides electrical isolation and reduces parasitic capacitance coupling between the adjacent conductive layers, enabling compact high-resolution pixel circuits without significant signal interference.
Data Source
AI summary
An array substrate, a display panel, and a display device are provided. The array substrate includes sub-pixel includes a pixel circuit, and the pixel circuit includes a light emitting element, a storage capacitor, a driving transistor, a data writing transistor, a data line and a first connection structure. The driving transistor is configured to control the light emitting element to emit light; the data line is connected to the first electrode of the data writing transistor and configured to provide a data signal for the data writing transistor; the data writing transistor is configured to write the data signal into the gate electrode of the driving transistor; and the first connection structure is connected to both the gate electrode of the driving transistor and a first electrode plate of the storage capacitor, and the first connection structure and the data line are provided in different layers.