OLED Display Substrate Pixel Layout for Low Delay and Voltage Drop

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Solution Overview

Problem

High-resolution OLED displays face challenges with signal delay, voltage drop, and non-uniform display due to increased pixel density, parasitic resistance, and parasitic capacitance, leading to issues like color shift and non-uniform display quality.

Innovation Solution

The display substrate incorporates a design with a 3T1C pixel circuit, including transistors and a storage capacitor, along with auxiliary electrode lines and optimized signal line arrangements to reduce resistance and capacitance loads, thereby alleviating voltage drops and signal delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If organic light-emitting materials are used to achieve high color purity and narrow spectral width, then display quality is improved, but the materials are easily oxidized and degraded by oxygen and moisture, reducing reliability

Engineering Contradiction:
Improvecolor purityVSAvoidmaterial stability
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

An encapsulation layer is introduced as an intermediary between the organic light-emitting material and the external environment. This encapsulation layer acts as a protective barrier that prevents oxygen and moisture from reaching and degrading the organic material, thereby maintaining both the color purity and long-term stability of the display device

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates an inert environment by encapsulating the organic light-emitting material in a protective layer that excludes reactive gases like oxygen and moisture. This inert environment prevents oxidation and degradation reactions, allowing the material to maintain its optical properties over time

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Ease of manufacture

If conventional sequential manufacturing processes are used, then manufacturing simplicity is maintained, but production time increases and productivity decreases

Engineering Contradiction:
Improveprocess simplicityVSAvoidproduction speed
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

Multiple manufacturing steps that were previously performed sequentially are merged into a single simultaneous deposition process. The gate electrode, active layer, and encapsulation layer are formed in one continuous operation rather than separate steps, significantly reducing production time while maintaining process simplicity through unified process control

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs preliminary patterning of the gate electrode before simultaneous deposition of the active layer and encapsulation layer. This preliminary action allows subsequent layers to be deposited conformally and selectively formed through etching, enabling complex structures to be built efficiently in fewer steps

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves display quality by reducing voltage drops and signal delays, minimizing color shift and non-uniformity, and enhancing the overall performance of high-resolution OLED displays.

Implementation Method 1

a self-aligned active layer forming method in which a gate electrode, on which a self-assembled monolayer is formed, is prepared; and an active layer is formed in a self-aligned manner with the gate electrode

Methodology Applied
Scientific EffectSelf-assembly: Self-Assembly

Implementation Method 2

an active layer and an encapsulation layer are formed in a self-aligned manner with the gate electrode by using a catalyst and performing chemical vapor deposition

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentEP4068265B1Display substrate and manufacturing method therefor, and display device
Publication Date: 2025.03.26 BOE TECHNOLOGY GROUP CO LTD
  • EP4068265B1 patent drawingFigure 1A~1B
  • EP4068265B1 patent drawingFigure 1C~1E
  • EP4068265B1 patent drawingFigure 2A

AI summary

A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate, and the sub-pixels are in an array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor; the second capacitor electrode and the first electrode of the second transistor are in a same layer and made of a same material, and are insulated from each other. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the gate electrode of the first transistor has a first side closest to the second capacitor electrode, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode. The display substrate can effectively improve the display effect.