OLED Pixel Layout With Offset Via Holes to Prevent Color Mixing

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Solution Overview

Problem

The manufacturing process of OLED display devices faces challenges in improving yield due to color mixing between adjacent pixel units, requiring finer masks and potentially reducing light emitting efficiency and pixel density.

Innovation Solution

The design includes a substrate with transistors, insulating layers, electrodes, and signal lines, where the distance between via holes is greater than the distance between signal lines, allowing for non-aligned connections between light emitting regions and data lines, preventing color mixing and maintaining pixel density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If pixel units with different colors are placed close together to increase pixel density, then the display resolution is improved, but color mixing between adjacent pixel units occurs

Engineering Contradiction:
Improvedisplay resolutionVSAvoidcolor mixing
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by deliberately designing the pixel units with non-uniform dimensions and orientations. Specifically, the first and second pixel units have different width-to-length ratios, and their long sides are oriented at different angles (e.g., parallel vs. perpendicular). This asymmetric arrangement creates geometric separation that prevents color mixing while maintaining high pixel density, resolving the contradiction between resolution and color mixing.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent introduces dimensional variation by arranging pixel units at different orientations in the plane. Instead of all pixel units being aligned in the same direction, the invention rotates certain pixel units (e.g., 90 degrees) relative to others. This multi-directional arrangement in the spatial dimension allows closer spacing without color overlap, improving resolution while preventing color mixing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-generated harmful factors

If finer masks are used for vapor depositions to separate adjacent pixel units, then color mixing is reduced, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvecolor mixingVSAvoidmask precision requirement
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-designing the pixel unit geometry and arrangement before the vapor deposition process. By establishing the asymmetric, multi-oriented pixel structure in advance, the invention eliminates the need for extremely fine masks during manufacturing. The geometric design itself prevents color mixing, simplifying the mask requirements and reducing manufacturing complexity while maintaining color separation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the geometric parameters of the pixel units, specifically the width-to-length ratios and orientation angles. By adjusting these parameters to create asymmetric arrangements, the invention achieves better color separation without requiring proportionally finer masks. This parameter optimization reduces the mask precision requirements and simplifies the manufacturing process.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If the distance between via holes is reduced to maintain pixel unit count, then display area is improved, but alignment precision requirements increase

Engineering Contradiction:
Improvedisplay areaVSAvoidvia hole alignment
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry in the via hole arrangement by positioning via holes at different locations relative to the pixel unit centers. Some via holes are offset in specific directions based on the asymmetric pixel geometry. This asymmetric via placement reduces the minimum distance between via holes while maintaining proper electrical connections, thereby increasing display area without proportionally increasing alignment difficulty.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent utilizes multi-dimensional positioning for via holes, placing them at different offsets in both x and y directions based on the oriented pixel unit geometry. By distributing via holes in multiple dimensional positions rather than uniform linear spacing, the invention reduces the minimum via hole distance while maintaining adequate alignment tolerances, thus improving display area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the manufacturing yield of OLED display devices by preventing color mixing and maintaining pixel density without reducing the number of pixel units, thus improving light emitting efficiency.

Implementation Method 1

the organic light emitting diode (OLED) display devices has advantages of: light weight, thin thickness, high brightness, fast response

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Implementation Method 2

light emitting layers capable of emitting different colors are formed by vapor depositions

Methodology Applied
Scientific EffectVapor deposition: Physical Vapour Deposition

Data Source

PatentUS20240292679A1Display device
Publication Date: 2024.08.29 RED OAK INNOVATIONS LTD
  • US20240292679A1 patent drawing
  • US20240292679A1 patent drawing
  • US20240292679A1 patent drawing

AI summary

A display device includes: a substrate; a first transistor and a second transistor disposed on the substrate; a first electrode and a second electrode, wherein the first electrode is electrically connected to the first transistor through a first via hole, and the second electrode is electrically connected to the second transistor through a second via hole; a first signal line disposed on the substrate and overlapped with the first electrode and the second electrode; and a second signal line disposed on the substrate and adjacent to the first signal line, wherein the first signal line and the second signal line extend along a first direction, wherein a distance between the first via hole and the second via hole along the first direction is greater than a distance between the first signal line and the second signal line along a second direction different the first direction.