OLED Pixel Circuit Shielding Layout for Uniform Brightness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The arrangement of thin film transistors and capacitors in OLED display panels causes signal overlap, leading to uneven brightness and reduced resolution, necessitating improved layout designs for signal shielding and space utilization.
Innovation Solution
A display panel design with a second gate layer incorporating a shielding layer that overlaps with alternating current power lines to shield signals, reducing noise and allowing for a more compact pixel layout, thereby achieving uniform brightness and high resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin film transistors and capacitors are arranged in the pixel driving circuit, then the display panel can function with driving capability, but signal overlap occurs causing uneven brightness and reduced resolution
Solution Approach 1:
A shielding layer is introduced as an intermediary element between the alternating current power line and the floating gate electrode. This shielding layer acts as a mediator that blocks the harmful electromagnetic signal from the power line from interfering with the floating gate electrode, thereby preventing brightness non-uniformity while preserving the necessary driving circuit functionality
Solution Approach 2:
The harmful electromagnetic signal from the alternating current power line is extracted and blocked by the shielding layer, separating the power signal path from the sensitive floating gate electrode. This extraction of the harmful interference allows the driving circuit to function reliably without causing brightness non-uniformity
2Reliability
If thin film transistors and capacitors are arranged in the pixel driving circuit, then the display panel can function with driving capability, but the pixel size increases reducing resolution
Solution Approach 1:
The shielding layer is integrated into the existing multi-layer structure of the display panel by adding it to the second gate layer. This dimensional integration allows the shielding function to be incorporated without significantly increasing the planar pixel area, thereby maintaining high resolution while providing necessary signal protection
Solution Approach 2:
The shielding layer is merged with the second gate layer structure, combining the gate function and shielding function in the same layer. This merging reduces the overall pixel area by eliminating the need for separate shielding structures, thereby improving resolution while maintaining driving capability
3Illumination intensity
If a shielding layer is added to block signal interference, then brightness uniformity improves, but device complexity increases
Solution Approach 1:
The second gate layer is given multiple functions: it serves as both the gate electrode layer for transistor operation and as the shielding layer for blocking electromagnetic interference. This multi-functionality reduces device complexity by eliminating the need for a separate dedicated shielding layer, while still achieving brightness uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively shields alternating current signals, preventing sudden potential changes and improving display quality by reducing pixel size for ultra-high resolution and uniform brightness.
Implementation Method 1
a second gate layer... includes a shielding layer; an orthographic projection of the shielding layer on the substrate covers at least a part of the overlapping region
Data Source
AI summary
The present application provides a display panel and a semiconductor device. The display panel is provided with a plurality of pixel light-emitting units and a plurality of driving circuits. An active layer is located on one side of a substrate and comprises a plurality of active regions. A first gate layer comprises a plurality of gates, and there is an overlapping area between the orthographic projections of the gates on the substrate and the orthographic projections of the corresponding active regions on the substrate. A second gate layer is located on the side of the first gate layer distant from the active layer and comprises a shielding layer. A first source-drain electrode layer is located on the side of the second gate layer distant from the first gate layer, and comprises a plurality of power lines arranged side by side.