OLED Pixel Circuit Layout Using Stacked Transistor Active Layers
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Solution Overview
Problem
The challenge of achieving high-resolution display devices with increasing pixel density in self-light emitting display devices, particularly in organic light emitting elements, where the size of individual pixels is becoming smaller, necessitating innovative design to enhance pixel density.
Innovation Solution
The display device incorporates a specific transistor configuration with a first and second transistor having different gate structures and gate electrodes defined by a common conductive line, along with a unique active area arrangement in different layers, allowing for increased pixel density through optimized transistor placement and timing of gate voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase pixel density, then resolution is improved, but transistor layout complexity increases
Solution Approach 1:
The patent applies dimensionality change by stacking active areas in different layers (first active area in first layer, second active area in second layer) to create a three-dimensional transistor layout. This vertical stacking approach allows multiple transistors to be integrated within a smaller planar footprint, thereby increasing pixel density and resolution without proportionally increasing layout complexity
Solution Approach 2:
The patent merges the gate electrodes of the second and third transistors into a single common conductive line. This consolidation reduces the number of separate gate structures required, simplifying the overall transistor layout while maintaining the functionality of multiple transistors in the pixel circuit, thus addressing the layout complexity issue
2Measurement precision
If pixel size is reduced to increase pixel density, then resolution is improved, but manufacturing precision requirements increase
Solution Approach 1:
By transitioning to a multi-layer active area configuration, the patent distributes transistor components across different vertical layers. This approach allows for larger effective transistor dimensions within each layer while achieving high pixel density through vertical stacking, thereby reducing the stringent manufacturing precision requirements that would otherwise be necessary for miniaturized planar transistors
3Quantity of substance
If transistor components are minimized for high pixel density, then pixel density is improved, but device functionality may be compromised
Solution Approach 1:
The patent maintains full device functionality by implementing complete transistor structures (including gate electrodes, active areas, and source/drain electrodes) across multiple layers. The vertical stacking ensures that each transistor retains its necessary functional components while achieving high pixel density through the three-dimensional arrangement, thus preventing functionality compromise
Solution Approach 2:
The common conductive line serving as gate electrodes for both the second and third transistors demonstrates multi-functionality. This single structure performs the gating function for multiple transistors simultaneously, reducing component count while maintaining the electrical control functionality required for high pixel density operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a high-resolution display device by enhancing pixel density, leveraging a compact design that maintains high luminance, contrast, and fast response speed while reducing power consumption.
Implementation Method 1
electrons and holes provided from the two electrodes may be recombined in the light emitting layer to generate excitons, the generated excitons may be changed from an excited state to a ground state, and light may be emitted
Data Source
AI summary
A display device includes, a light emitting element including a first electrode, a light emitting layer, and a second electrode, a first transistor including a first source electrode, a first active area, a first drain electrode, and a first gate electrode, a second transistor including a second source electrode, a second active area, a second drain electrode, and a second gate electrode, and a third transistor including a third source electrode, a third active area, a third drain electrode, and a third gate electrode, wherein the first source electrode is connected to the first electrode, the second source electrode is connected to the first gate electrode, the third drain electrode is connected to the first source electrode, the second gate electrode and the third gate electrode are defined by a same conductive line, and the second active area and the third active area are disposed in different layers.